am79c960 Advanced Micro Devices, am79c960 Datasheet - Page 49

• Manufacturer Part Number: am79c960
• Description: Pcnettm-isa Single-chip Ethernet Controller
• Manufacturer: Advanced Micro Devices

capability is desirable since two 8-bit accesses take the
same amount of time as four 16-bit accesses.
All accesses to 8-bit resources (which do not return
MEMCS16 or IOCS16) use SD0-7. If an odd byte is ac-
cessed, the Current Master swap buffer turns on. During
an odd byte read the swap buffer copies the data from
SD0-7 to the high byte. During an odd byte write the Cur-
rent Master swap buffer copies the data from the high
byte to SD0-7. The PCnet-ISA controller can be config-
ured to be an 8-bit I/O resource even in a 16-bit system;
this is accomplished by disconnecting IOCS16 from the
ISA bus and tying IOCS16 to ground. It is recommended
that the PCnet-ISA controller be hardware configured
for 8-bit only I/O bus cycles for maximum compatibility
with PC/AT clone motherboards.
When the PCnet-ISA controller is in an 8-bit system
such as a PC/XT, SBHE and IOCS16 must be left un-
connected (these signals do not exist in the PC/XT).
This will force ALL resources (I/O and memory) to sup-
port only 8-bit bus cycles. The PCnet-ISA controller will
function in an 8-bit system only if configured for Shared
Memory Mode.
Accesses to 16-bit resources (which do return
MEMCS16 or IOCS16) use either or both SD0-7 and
SD8-15. A word access is indicated by A0=0 and
SBHE=0 and data is transferred on all 16 data lines. An
even byte access is indicated by A0=0 and SBHE=1 and
*Motherboard SWAP logic drives
R/W
WR
WR
WR
WR
WR
RD
RD
RD
RD
RD
A0
0
1
0
1
0
0
1
0
1
0
SBHE
1
0
0
0
0
1
0
0
0
0
CS16
Table: ISA Bus Accesses
1
1
0
0
1
1
0
0
x
x
P R E L I M I N A R Y
Am79C960
Master
Master
Master
Float*
Slave
Slave
Slave
Slave
D0-7
Float
Float
data is transferred on SD0-7. An odd-byte access is indi-
cated by A0=1 and SBHE=0 and data is transferred on
SD8-15. It is illegal to have A0=1 and SBHE=1 in any
bus cycle. The PCnet-ISA controller returns only
IOCS16; MEMCS16 must be generated by external
hardware if desired. The use of MEMCS16 applies only
to Shared Memory Mode.
The following table describes all possible types of ISA
bus accesses, including Permanent Master as Current
Master and PCnet-ISA controller as Current Master.
The PCnet-ISA controller will not work with 8-bit mem-
ory while it is Current Master. Any descriptions of 8-bit
memory accesses are for when the Permanent Master
is Current Master.
The two byte columns (D0-7 and D8-15) indicate
whether the bus master or slave is driving the byte.
CS16 is a shorthand for MEMCS16 and IOCS16.
Bus Master Mode
The PCnet-ISA controller can be configured as a Bus
Master only in systems that support bus mastering. In
addition, the system is assumed to support 16-bit
memory (DMA) cycles (the PCnet-ISA controler does
not use the MEMCS16 signal on the ISA bus). This does
not preclude the PCnet-ISA controller from doing 8-bit
I/O transfers. The PCnet-ISA controller will not function
as a bus master in 8-bit platforms such as the PC/XT.
Master
Master
Master
Master
D8-15
Float*
Slave
Slave
Float
Float
Float
Low byte RD
High byte RD with swap
16-Bit RD converted to
low byte RD
High byte RD
16-Bit RD
Low byte WR
High byte WR with swap
16-Bit WR converted to
low byte WR
High byte WR
16-Bit WR
Comments
AMD
1-391