am79c960 Advanced Micro Devices, am79c960 Datasheet - Page 70

• Manufacturer Part Number: am79c960
• Description: Pcnettm-isa Single-chip Ethernet Controller
• Manufacturer: Advanced Micro Devices

CSR68-69: Transmit Status Temporary Storage
Bit
31-0
CSR70-71: Temporary Storage
Bit
31-0
CSR72: Receive Ring Counter
Bit
15-0
CSR74: Transmit Ring Counter
Bit
15-0
CSR76: Receive Ring Length
Bit
15-0
1-412
AMD
RCVRC
XMTRC
XSTMP
RCVRL
TMP8
Name
Name
Name
Name
Name
Transmit Status Temporary Stor-
age location.
Read/write accessible only when
STOP bit is set.
Temporary Storage location.
Read/write accessible only when
STOP bit is set.
Receive Ring Counter location.
Contains a Two’s complement
binary number used to number
the current receive descriptor.
This counter interprets the value
in CSR76 as pointing to the first
descriptor; a two’s complement
value of -1 (FFFFh) corresponds
to the last descriptor in the ring.
Read/write accessible only when
STOP bit is set.
Transmit Ring Counter location.
Contains a Two’s complement
binary number used to number
the current transmit descriptor.
This counter interprets the value
in CSR78 as pointing to the first
descriptor; a two’s complement
value of -1 (FFFFh) corresponds
to the last descriptor in the ring.
Read/write accessible only when
STOP bit is set.
Receive Ring Length. Contains a
Two’s complement binary num-
ber of the receive descriptor ring
length. This register is initialized
during the PCnet-ISA controller
initialization routine based on the
Description
Description
Description
Description
Description
P R E L I M I N A R Y
Am79C960
CSR78: Transmit Ring Length
Bit
15-0
CSR80: Burst and FIFO Threshold Control
Bit
15-14
13-12RCVFW[1:0]
XMTRL
Name
Name
RES
value in the RLEN field of the
initialization block. This register
can be manually altered; the ac-
tual receive ring length is defined
by the current value in this
register.
Read/write accessible only when
STOP bit is set.
Transmit Ring Length. Contains
the two’s complement of the
transmit descriptor ring length.
This register is initialized during
the PCnet-ISA controller
initialization routine based on the
value in the TLEN field of the ini-
tialization block. This register can
be manually altered; the actual
transmit ring length is defined by
the current value in this register.
Read/write accessible only when
STOP bit is set.
Reserved locations. Read as
ones. Written as zero.
Receive
RCVFW controls the point at
which ISA bus receive DMA is re-
quested in relation to the number
of received bytes in the receive
FIFO. RCVFW specifies the
number of bytes which must be
present (once the frame has
been verified as a non-runt) be-
fore receive DMA is requested.
Note however that in order for re-
ceive DMA to be performed for a
new frame, at least 64 bytes must
have been received. This effec-
tively avoids having to react to
receive frames which are runts or
suffer a collision during the slot
time (512 bit times). If the Runt
Packet Accept feature is en-
abled, receive DMA will be
requested as soon as either the
RCVFW threshold is reached, or
a complete valid receive frame is
detected (regardless of length).
RCVFW is set to a value of 10b
(64 bytes) after RESET.
Read/write accessible only when
STOP bit is set.
Description
Description
FIFO
Watermark.