am79c960 Advanced Micro Devices, am79c960 Datasheet - Page 40

• Manufacturer Part Number: am79c960
• Description: Pcnettm-isa Single-chip Ethernet Controller
• Manufacturer: Advanced Micro Devices

1-382
MAC Engine will abort the transmission, append the jam
sequence, and set the LCOL bit. No retry attempt will be
scheduled on detection of a late collision, and the FIFO
will be flushed.
The IEEE 802.3 Standard requires use of a “truncated
binary exponential backoff” algorithm which provides a
controlled pseudo-random mechanism to enforce the
collision backoff interval, before re-transmission is
attempted.
The PCnet-ISA controller provides an alternative algo-
rithm, which suspends the counting of the slot time/IPG
during the time that receive carrier sense is detected.
This algorithm aids in networks where large numbers of
nodes are present, and numerous nodes can be in
collision. The algorithm effectively accelerates the
increase in the backoff time in busy networks, and al-
lows nodes not involved in the collision to access the
channel while the colliding nodes await a reduction in
channel activity. Once channel activity is reduced, the
nodes resolving the collision time out their slot time
counters as normal.
Manchester Encoder/Decoder
(MENDEC)
The integrated Manchester Encoder/Decoder provides
the PLS (Physical Layer Signaling) functions required
for a fully compliant IEEE 802.3 station. The MENDEC
provides the encoding function for data to be transmitted
on the network using the high accuracy on-board oscil-
lator, driven by either the crystal oscillator or an external
CMOS-level compatible clock. The MENDEC also pro-
vides the decoding function from data received from the
network. The MENDEC contains a Power On Reset
(POR) circuit, which ensures that all analog portions of
the PCnet-ISA controller are forced into their correct
state during power-up, and prevents erroneous data
transmission and/or reception during this time.
See ANSI/IEEE Std 802.3-1990 Edition, 4.2.3.2.5:
“At the end of enforcing a collision (jamming),
the CSMA/CD sublayer delays before attempt-
ing to re-transmit the frame. The delay is an
integer multiple of slotTime. The number of slot
times to delay before the nth re-transmission
attempt is chosen as a uniformly distributed
random integer r in the range:
AMD
0
r < 2
k
, where k = min (n,10).”
P R E L I M I N A R Y
Am79C960
External Crystal Characteristics
When using a crystal to drive the oscillator, the crystal
specification shown in the table may be used to ensure
less than 0.5 ns jitter at DO .
* Requires trimming crystal spec; no trim is 50 ppm total
External Clock Drive Characteristics
When driving the oscillator from an external clock
source, XTAL2 must be left floating (unconnected). An
external clock having the following characteristics must
be used to ensure less than 0.5 ns jitter at DO :
MENDEC Transmit Path
The transmit section encodes separate clock and NRZ
data input signals into a standard Manchester encoded
serial bit stream. The transmit outputs (DO ) are de-
signed to operate into terminated transmission lines.
When operating into a 78
line, the transmit signaling meets the required output
levels and skew for Cheapernet, Ethernet, and
IEEE-802.3.
Clock Frequency:
Rise/Fall Time (tR/tF):
XTAL1 HIGH/LOW Time
XTAL1 Falling Edge to
Falling Edge Jitter:
Parameter
1.Parallel Resonant
2.Resonant Frequency Error
3.Change in Resonant Frequency
4.Crystal Capacitance
5.Motional Crystal
6.Series Resistance
7.Shunt Capacitance
8.Drive Level
(tHIGH/tLOW):
Frequency
(CL = 20 pF)
With Respect To Temperature
Capacitance (C1)
(0 – 70 C; CL = 20 pF)*
Table : External Crystal Characteristics
Min
–50
–40
terminated transmission
20 MHz 0.01%
< 6 ns from 0.5 V
to V
20 ns min
< 0.2 ns at
2.5 V input (V
DD
0.022
Nom
20
–0.5
TBD
Max
+50
+40
20
25
7
DD
/2)
Units
PPM
PPM
MHz
mW
pF
pF
pF