am79c960 Advanced Micro Devices, am79c960 Datasheet - Page 78

• Manufacturer Part Number: am79c960
• Description: Pcnettm-isa Single-chip Ethernet Controller
• Manufacturer: Advanced Micro Devices

The Logical Address Filter is used in multicast address-
ing schemes. The acceptance of the incoming frame
based on the filter value indicates that the message may
be intended for the node. It is the node’s responsibility to
determine if the message is actually intended for the
node by comparing the destination address of the stored
message with a list of acceptable logical addresses.
If the Logical Address Filter is loaded with all zeroes and
promiscuous mode is disabled, all incoming logical ad-
dresses except broadcast will be rejected.
The Broadcast address, which is all ones, does not go
through the Logical Address Filter and is handled as
follows:
1) If the Disable Broadcast Bit is cleared, the
2) If the Disable Broadcast Bit is set and promiscuous
3) If the Disable Broadcast Bit is set and promiscous
If external loopback is used, the FCS logic must be allo-
cated to the receiver (by setting the DXMTFCS bit in
CSR15, and clearing the ADD_FCS bit in TMD1) when
using multicast addressing.
PADR
This 48-bit value represents the unique node address
assigned by the IEEE and used for internal address
comparison. PADR[0] is the first address bit transmitted
on the wire, and must be zero. The six-byte nomencla-
ture used by the IEEE maps to the PCnet-ISA controller
PADR register as follows: the first byte comprises
PADR[7:0], with PADR[0] being the least significant bit
of the byte. The second IEEE byte maps to PADR[15:8],
again from LSbit to MSbit, and so on. The sixth byte
maps to PADR[47:40], the LSbit being PADR[40].
1-420
broadcast address is accepted.
mode is enabled, the broadcast address is
accepted.
mode is disabled, the broadcast address is rejected.
AMD
MATCH = 1:
MATCH = 0:
47
Destination Address
Received Message
Packet Accepted
Packet Rejected
1 0
1
P R E L I M I N A R Y
Address Match Logic
GEN
CRC
SEL
Am79C960
MODE
The mode register in the initialization block is copied into
CSR15 and interpreted according to the description of
CSR15.
Receive Descriptors
The Receive Descriptor Ring Entries (RDREs) are com-
posed of 4 receive message fields (RMD0-3). Together
they contain the following information:
RMD0
Holds LADR [15:0]. This is combined with HADR [7:0] in
RMD1 to form the 24-bit address of the buffer pointed to
by this descriptor table entry. There are no restrictions
on buffer byte alignment or length.
RMD1
Bit
15
The address of the actual message data buffer in
user (host) memory.
The length of that message buffer.
Status information indicating the condition of the
buffer. The eight most significant bits of RMD1
(RMD1[15:0]) are collectively termed the STATUS
of the receive descriptor.
31
Name
OWN
32-Bit Resultant CRC
64
6
26
63
This bit indicates that the de-
scriptor entry is owned by the
host
PCnet-ISA controller (OWN=1).
The PCnet-ISA controller clears
the OWN bit after filling the buffer
pointed to by the descriptor entry.
The host sets the OWN bit after
emptying the buffer. Once the
PCnet-ISA controller or host has
relinquished ownership of a
MUX
(OWN=0)
(LADRF)
Address
Logical
Filter
Description
0
or
16907B-15
MATCH
0
by
the