am79c960 Advanced Micro Devices, am79c960 Datasheet - Page 73

• Manufacturer Part Number: am79c960
• Description: Pcnettm-isa Single-chip Ethernet Controller
• Manufacturer: Advanced Micro Devices

CSR96-97: Bus Interface Scratch Register 0
Bit
31-0
CSR98-99: Bus Interface Scratch Register 1
Bit
31-0
CSR104-105: SWAP
Bit
31-0
Internal Write
Lower 16-Bit
32-Bit word
(CSR104)
Operation
SWAP
SCR0
SCR1
Name
Name
Name
SRC[31:16]
SRC[15:0]
SRC[15:8]
SRC[7:0]
This register is shared between
the Buffer Management Unit and
the Bus Interface Unit. All De-
scriptor Data communications
between the BIU and BMU are
written and read through SCR0
and SCR1 registers. The SCR0
register is undefined until written.
Read/write accessible only when
STOP bit is set.
This register is shared between
the Buffer Management Unit and
the Bus Interface Unit. All De-
scriptor Data communications
between the BIU and BMU are
written and read through SCR0
and SCR1 registers.
Read/write accessible only when
STOP bit is set.
This register performs word and
byte swapping depending upon if
32-bit or 16-bit internal write op-
erations are performed. This
register is used internally by the
BIU/BMU as a word or byte
swapper. The swap register can
perform 32-bit operations that
the PC can not; the register is ex-
ternally
reasons only. CSR104 holds the
lower 16 bits and CSR105 holds
the upper 16 bits.
The swap function is defined as
follows:
Read/write accessible only when
STOP bit is set.
SWAP Register Result
accessible
Description
Description
Description
SWAP[15:0]
SWAP[31:16]
SWAP[ 7: 0]
SWAP[15:8]
P R E L I M I N A R Y
for
test
Am79C960
CSR108-109: Buffer Management Scratch
Bit
31-0 BMSCR
CSR112: Missed Frame Count
Bit
15-0
CSR114: Receive Collision Count
Bit
15-0
CSR124: Buffer Management Unit Test
Bit
RCVCC
Name
Name
Name
Name
MFC
The Buffer Management Scratch
register is used for assembling
Receive and Transmit Status.
This register is also used as the
primary scan register for Buffer
Management
BMSCR register is undefined un-
til written.
Read/write accessible only when
STOP bit is set.
Counts the number of missed
frames.
This register is always readable
and is cleared by STOP.
A write to this register performs
an increment when the ENTST
bit in CSR4 is set.
When MFC is all 1’s (65535) and
a missed frame occurs, MFC in-
crements to 0 and sets MFC0 bit
(CSR4.9).
Counts the number of Receive
collisions seen, regular and late.
This register is always readable
and is cleared by STOP.
A write to this register performs
an increment when the ENTST
bit in CSR4 is set.
When RCVCC is all 1’s (65535)
and a receive collision occurs,
RCVCC increments to 0 and sets
RCVCC0 bit (CSR4.5)
This register is used to place the
BMU/BIU into various test modes
to support Test/Debug. This reg-
ister is writeable when the
ENTST bit in CSR4 is set.
Description
Description
Description
Description
Test
AMD
Modes.
1-415