S9S12G64F0MLF Freescale Semiconductor, S9S12G64F0MLF Datasheet - Page 1008

• Manufacturer Part Number: S9S12G64F0MLF
• Description: 16-bit Microcontrollers - MCU S12 Core,64kFlash,Au
• Manufacturer: Freescale Semiconductor

Specifications of S9S12G64F0MLF

• Rohs: yes
• Core: S12
• Processor Series: MC9S12G
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 25 MHz
• Program Memory Size: 64 KB
• Data Ram Size: 2 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3.13 V to 5.5 V
• Operating Temperature Range: - 40 C to + 125 C
• Package / Case: LQFP-48
• Mounting Style: SMD/SMT

96 KByte Flash Module (S12FTMRG96K1V1)
28.4.3
IFR is an internal NVM resource readable by CPU , when NVMRES is active. The IFR fields are shown
in
The NVMRES global address map is shown in
28.4.4
Flash command operations are used to modify Flash memory contents.
The next sections describe:
28.4.4.1
Prior to issuing any Flash program or erase command after a reset, the user is required to write the
FCLKDIV register to divide BUSCLK down to a target FCLK of 1 MHz.
values for the FDIV field based on BUSCLK frequency.
When the FCLKDIV register is written, the FDIVLD bit is set automatically. If the FDIVLD bit is 0, the
FCLKDIV register has not been written since the last reset. If the FCLKDIV register has not been written,
any Flash program or erase command loaded during a command write sequence will not execute and the
ACCERR bit in the FSTAT register will set.
28.4.4.2
The Memory Controller will launch all valid Flash commands entered using a command write sequence.
Before launching a command, the ACCERR and FPVIOL bits in the FSTAT register must be clear (see
Section
sequence. If CCIF is 0, the previous command write sequence is still active, a new command write
sequence cannot be started, and all writes to the FCCOB register are ignored.
1010
Table
•
•
•
How to write the FCLKDIV register that is used to generate a time base (FCLK) derived from
BUSCLK for Flash program and erase command operations
The command write sequence used to set Flash command parameters and launch execution
Valid Flash commands available for execution, according to MCU functional mode and MCU
security state.
28.3.2.7) and the CCIF flag should be tested to determine the status of the current command write
28-5.
Internal NVM resource (NVMRES)
Flash Command Operations
Writing the FCLKDIV Register
Command Write Sequence
Programming or erasing the Flash memory cannot be performed if the bus
clock runs at less than 0.8 MHz. Setting FDIV too high can destroy the Flash
memory due to overstress. Setting FDIV too low can result in incomplete
programming or erasure of the Flash memory cells.
MC9S12G Family Reference Manual,
Table
NOTE
28-6.
Rev.1.23
Table 28-8
shows recommended
Freescale Semiconductor