S9S12G64F0MLF Freescale Semiconductor, S9S12G64F0MLF Datasheet - Page 568

• Manufacturer Part Number: S9S12G64F0MLF
• Description: 16-bit Microcontrollers - MCU S12 Core,64kFlash,Au
• Manufacturer: Freescale Semiconductor

Specifications of S9S12G64F0MLF

• Rohs: yes
• Core: S12
• Processor Series: MC9S12G
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 25 MHz
• Program Memory Size: 64 KB
• Data Ram Size: 2 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3.13 V to 5.5 V
• Operating Temperature Range: - 40 C to + 125 C
• Package / Case: LQFP-48
• Mounting Style: SMD/SMT

Analog-to-Digital Converter (ADC12B16CV2)
16.4
The ADC12B16C consists of an analog sub-block and a digital sub-block.
16.4.1
The analog sub-block contains all analog electronics required to perform a single conversion. Separate
power supplies VDDA and VSSA allow to isolate noise of other MCU circuitry from the analog sub-block.
16.4.1.1
The Sample and Hold Machine controls the storage and charge of the sample capacitor to the voltage level
of the analog signal at the selected ADC input channel.
During the sample process the analog input connects directly to the storage node.
The input analog signals are unipolar and must be within the potential range of VSSA to VDDA.
During the hold process the analog input is disconnected from the storage node.
16.4.1.2
The analog input multiplexer connects one of the 16 external analog input channels to the sample and hold
machine.
16.4.1.3
The A/D Machine performs analog to digital conversions. The resolution is program selectable to be either
8 or 10 or 12 bits. The A/D machine uses a successive approximation architecture. It functions by
comparing the sampled and stored analog voltage with a series of binary coded discrete voltages.
By following a binary search algorithm, the A/D machine identifies the discrete voltage that is nearest to
the sampled and stored voltage.
When not converting the A/D machine is automatically powered down.
Only analog input signals within the potential range of VRL to VRH (A/D reference potentials) will result
in a non-railed digital output code.
16.4.2
This subsection describes some of the digital features in more detail. See
Descriptions”
16.4.2.1
The external trigger feature allows the user to synchronize ATD conversions to an external event rather
than relying only on software to trigger the ATD module when a conversion is about to take place. The
external trigger signal (out of reset ATD channel 15, configurable in ATDCTL1) is programmable to be
570
Functional Description
Analog Sub-Block
Digital Sub-Block
Sample and Hold Machine
Analog Input Multiplexer
Analog-to-Digital (A/D) Machine
External Trigger Input
for all details.
MC9S12G Family Reference Manual,
Rev.1.23
Section 16.3.2, “Register
Freescale Semiconductor