S9S12G64F0MLF Freescale Semiconductor, S9S12G64F0MLF Datasheet - Page 404

• Manufacturer Part Number: S9S12G64F0MLF
• Description: 16-bit Microcontrollers - MCU S12 Core,64kFlash,Au
• Manufacturer: Freescale Semiconductor

Specifications of S9S12G64F0MLF

• Rohs: yes
• Core: S12
• Processor Series: MC9S12G
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 25 MHz
• Program Memory Size: 64 KB
• Data Ram Size: 2 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3.13 V to 5.5 V
• Operating Temperature Range: - 40 C to + 125 C
• Package / Case: LQFP-48
• Mounting Style: SMD/SMT

S12 Clock, Reset and Power Management Unit (S12CPMU)
Several examples of PLL divider settings are shown in
optimum stability and shortest lock time:
The phase detector inside the PLL compares the feedback clock (FBCLK = VCOCLK/(SYNDIV+1)) with
the reference clock (REFCLK = (IRC1M or OSCCLK)/(REFDIV+1)). Correction pulses are generated
based on the phase difference between the two signals. The loop filter alters the DC voltage on the internal
filter capacitor, based on the width and direction of the correction pulse, which leads to a higher or lower
VCO frequency.
The user must select the range of the REFCLK frequency (REFFRQ[1:0] bits) and the range of the
VCOCLK frequency (VCOFRQ[1:0] bits) to ensure that the correct PLL loop bandwidth is set.
The lock detector compares the frequencies of the FBCLK and the REFCLK. Therefore the speed of the
lock detector is directly proportional to the reference clock frequency. The circuit determines the lock
condition based on this comparison.
If PLL LOCK interrupt requests are enabled, the software can wait for an interrupt request and for instance
check the LOCK bit. If interrupt requests are disabled, software can poll the LOCK bit continuously
(during PLL start-up) or at periodic intervals. In either case, only when the LOCK bit is set, the VCOCLK
will have stabilized to the programmed frequency.
406
4MHz
f
•
•
•
•
•
osc
off
off
Use lowest possible f
Use highest possible REFCLK frequency f
The LOCK bit is a read-only indicator of the locked state of the PLL.
The LOCK bit is set when the VCO frequency is within the tolerance ∆
the VCO frequency is out of the tolerance ∆
Interrupt requests can occur if enabled (LOCKIE = 1) when the lock condition changes, toggling
the LOCK bit.
REFDIV[3:
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0]
1MHz
1MHz
4MHz
f
REF
REFFRQ[1:0] SYNDIV[5:0]
VCO
Table 10-25. Examples of PLL Divider Settings
00
00
01
MC9S12G Family Reference Manual,
/ f
REF
ratio (SYNDIV value).
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$05
REF
unl
50MHz
50MHz
48MHz
.
.
f
VCO
Table
VCOFRQ[1:0]
10-25. The following rules help to achieve
Rev.1.23
01
01
00
POSTDIV
[4:0]
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Lock
and is cleared when
Freescale Semiconductor
12.5MHz
50MHz
48MHz
f
PLL
6.25MHz
25MHz
24MHz
f
bus