S9S12G64F0MLF Freescale Semiconductor, S9S12G64F0MLF Datasheet - Page 1154

• Manufacturer Part Number: S9S12G64F0MLF
• Description: 16-bit Microcontrollers - MCU S12 Core,64kFlash,Au
• Manufacturer: Freescale Semiconductor

Specifications of S9S12G64F0MLF

• Rohs: yes
• Core: S12
• Processor Series: MC9S12G
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 25 MHz
• Program Memory Size: 64 KB
• Data Ram Size: 2 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3.13 V to 5.5 V
• Operating Temperature Range: - 40 C to + 125 C
• Package / Case: LQFP-48
• Mounting Style: SMD/SMT

240 KByte Flash Module (S12FTMRG240K2V1)
31.3.2.9
The FPROT register defines which P-Flash sectors are protected against program and erase operations.
1
The (unreserved) bits of the FPROT register are writable with the restriction that the size of the protected
region can only be increased (see
During the reset sequence, the FPROT register is loaded with the contents of the P-Flash protection byte
in the Flash configuration field at global address 0x3_FF0C located in P-Flash memory (see
as indicated by reset condition ‘F’ in
during the reset sequence, the upper sector of the P-Flash memory must be unprotected, then the P-Flash
protection byte must be reprogrammed. If a double bit fault is detected while reading the P-Flash phrase
containing the P-Flash protection byte during the reset sequence, the FPOPEN bit will be cleared and
remaining bits in the FPROT register will be set to leave the P-Flash memory fully protected.
Trying to alter data in any protected area in the P-Flash memory will result in a protection violation error
and the FPVIOL bit will be set in the FSTAT register. The block erase of a P-Flash block is not possible if
any of the P-Flash sectors contained in the same P-Flash block are protected.
1156
FPHS[1:0]
Loaded from IFR Flash configuration field, during reset sequence.
FPOPEN
FPHDIS
Offset Module Base + 0x0008
RNV[6]
Reset
Field
4–3
7
6
5
W
R
FPOPEN
Flash Protection Operation Enable — The FPOPEN bit determines the protection function for program or
erase operations as shown in
0 When FPOPEN is clear, the FPHDIS and FPLDIS bits define unprotected address ranges as specified by the
1 When FPOPEN is set, the FPHDIS and FPLDIS bits enable protection for the address range specified by the
Reserved Nonvolatile Bit — The RNV bit should remain in the erased state for future enhancements.
Flash Protection Higher Address Range Disable — The FPHDIS bit determines whether there is a
protected/unprotected area in a specific region of the P-Flash memory ending with global address 0x3_FFFF.
0 Protection/Unprotection enabled
1 Protection/Unprotection disabled
Flash Protection Higher Address Size — The FPHS bits determine the size of the protected/unprotected area
in P-Flash memory as shown
P-Flash Protection Register (FPROT)
F
7
1
corresponding FPHS and FPLS bits
corresponding FPHS and FPLS bits
RNV6
F
= Unimplemented or Reserved
6
1
Figure 31-13. Flash Protection Register (FPROT)
MC9S12G Family Reference Manual,
Table 31-17. FPROT Field Descriptions
Section 31.3.2.9.1, “P-Flash Protection Restrictions,” and Table
FPHDIS
Figure
inTable
Table 31-18
F
5
1
31-19. The FPHS bits can only be written to while the FPHDIS bit is set.
31-13. To change the P-Flash protection that will be loaded
for the P-Flash block.
F
4
1
FPHS[1:0]
Description
F
3
1
Rev.1.23
FPLDIS
F
2
1
Freescale Semiconductor
F
1
1
FPLS[1:0]
Table
31-21).
F
31-4)
0
1