S9S12G64F0MLF Freescale Semiconductor, S9S12G64F0MLF Datasheet - Page 596

• Manufacturer Part Number: S9S12G64F0MLF
• Description: 16-bit Microcontrollers - MCU S12 Core,64kFlash,Au
• Manufacturer: Freescale Semiconductor

Specifications of S9S12G64F0MLF

• Rohs: yes
• Core: S12
• Processor Series: MC9S12G
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 25 MHz
• Program Memory Size: 64 KB
• Data Ram Size: 2 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 3.13 V to 5.5 V
• Operating Temperature Range: - 40 C to + 125 C
• Package / Case: LQFP-48
• Mounting Style: SMD/SMT

Freescale’s Scalable Controller Area Network (S12MSCANV3)
1
2
18.3.2.6
This register contains the interrupt enable bits for the interrupt flags described in the CANRFLG register.
1
598
Module Base + 0x0005
Redundant Information for the most critical CAN bus status which is “bus-off”. This only occurs if the Tx error counter exceeds
a number of 255 errors. Bus-off affects the receiver state. As soon as the transmitter leaves its bus-off state the receiver state
skips to RxOK too. Refer also to TSTAT[1:0] coding in this register.
To ensure data integrity, do not read the receive buffer registers while the RXF flag is cleared. For MCUs with dual CPUs,
reading the receive buffer registers while the RXF flag is cleared may result in a CPU fault condition.
Read: Anytime
Write: Anytime when not in initialization mode
OVRIF
Field
RXF
1
0
Reset:
2
W
R
Overrun Interrupt Flag — This flag is set when a data overrun condition occurs. If not masked, an error interrupt
is pending while this flag is set.
0
1
Receive Buffer Full Flag — RXF is set by the MSCAN when a new message is shifted in the receiver FIFO.
This flag indicates whether the shifted buffer is loaded with a correctly received message (matching identifier,
matching cyclic redundancy code (CRC) and no other errors detected). After the CPU has read that message
from the RxFG buffer in the receiver FIFO, the RXF flag must be cleared to release the buffer. A set RXF flag
prohibits the shifting of the next FIFO entry into the foreground buffer (RxFG). If not masked, a receive interrupt
is pending while this flag is set.
0
1
MSCAN Receiver Interrupt Enable Register (CANRIER)
WUPIE
The CANRIER register is held in the reset state when the initialization mode
is active (INITRQ=1 and INITAK=1). This register is writable when not in
initialization mode (INITRQ=0 and INITAK=0).
The RSTATE[1:0], TSTATE[1:0] bits are not affected by initialization
mode.
0
7
No data overrun condition
A data overrun detected
No new message available within the RxFG
The receiver FIFO is not empty. A new message is available in the RxFG
Figure 18-9. MSCAN Receiver Interrupt Enable Register (CANRIER)
Table 18-11. CANRFLG Register Field Descriptions (continued)
CSCIE
6
0
MC9S12G Family Reference Manual,
RSTATE1
0
5
RSTATE0
NOTE
4
0
Description
TSTATE1
0
3
Rev.1.23
TSTATE0
2
0
Access: User read/write
Freescale Semiconductor
OVRIE
0
1
RXFIE
0
0
1