MT47H128M8HQ-3 L:G Micron Technology Inc, MT47H128M8HQ-3 L:G Datasheet - Page 116

• Manufacturer Part Number: MT47H128M8HQ-3 L:G
• Description: IC DDR2 SDRAM 1GBIT 3NS 60FBGA
• Manufacturer: Micron Technology Inc
• Type: DDR2 SDRAMr

Specifications of MT47H128M8HQ-3 L:G

• Format - Memory: RAM
• Memory Type: DDR2 SDRAM
• Memory Size: 1G (128M x 8)
• Speed: 3ns
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 60-FBGA
• Organization: 128Mx8
• Density: 1Gb
• Address Bus: 17b
• Access Time (max): 450ps
• Maximum Clock Rate: 667MHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: FBGA
• Operating Temp Range: 0C to 85C
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 135mA
• Pin Count: 60
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 69: Power-Down
PDF: 09005aef821ae8bf
1GbDDR2.pdf – Rev. T 02/10 EN
DQS, DQS#
Command
Address
CK#
CKE
DM
DQ
CK
Valid 1
Valid
T1
Notes:
t CK
power-down
mode 6
Enter
1. If this command is a PRECHARGE (or if the device is already in the idle state), then the
2.
3.
4.
5.
6. No column accesses are allowed to be in progress at the time power-down is entered. If
NOP
T2
power-down mode shown is precharge power-down. If this command is an ACTIVATE
(or if at least one row is already active), then the power-down mode shown is active power-
down.
t
clock edges. CKE must remain at the valid input level the entire time it takes to achieve
the three clocks of registration. Thus, after any CKE transition, CKE may not transition
from its valid level during the time period of
during its
t
READ command.
t
ted via MR (bit 12 = 0).
t
ted via MR (bit 12 = 1).
the DLL was not in a locked state when CKE went LOW, the DLL must be reset after
exiting power-down mode for proper READ operation.
t CH
CKE (MIN) of three clocks means CKE must be registered on three consecutive positive
XP timing is used for exit precharge power-down and active power-down to any non-
XARD timing is used for exit active power-down to READ command if fast exit is selec-
XARDS timing is used for exit active power-down to READ command if slow exit is selec-
t CL
t
IS and
T3
t CKE (MIN) 2
t
IH window.
T4
116
t IH
power-down
t IS
Micron Technology, Inc. reserves the right to change products or specifications without notice.
mode
NOP
Exit
T5
1Gb: x4, x8, x16 DDR2 SDRAM
t
IS + 2 ×
t XP 3 , t XARD 4
t XARDS 5
NOP
T6
t
t CKE (MIN) 2
CK +
t
IH. CKE must not transition
Power-Down Mode
© 2004 Micron Technology, Inc. All rights reserved.
Valid
Valid
T7
t IH
Don’t Care
Valid
Valid
T8