MT47H128M8HQ-3 L:G Micron Technology Inc, MT47H128M8HQ-3 L:G Datasheet - Page 40

• Manufacturer Part Number: MT47H128M8HQ-3 L:G
• Description: IC DDR2 SDRAM 1GBIT 3NS 60FBGA
• Manufacturer: Micron Technology Inc
• Type: DDR2 SDRAMr

Specifications of MT47H128M8HQ-3 L:G

• Format - Memory: RAM
• Memory Type: DDR2 SDRAM
• Memory Size: 1G (128M x 8)
• Speed: 3ns
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 60-FBGA
• Organization: 128Mx8
• Density: 1Gb
• Address Bus: 17b
• Access Time (max): 450ps
• Maximum Clock Rate: 667MHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: FBGA
• Operating Temp Range: 0C to 85C
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 135mA
• Pin Count: 60
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PDF: 09005aef821ae8bf
1GbDDR2.pdf – Rev. T 02/10 EN
31. V
32. For each input signal—not the group collectively.
33. There are two sets of values listed for command/address:
34. This is applicable to READ cycles only. WRITE cycles generally require additional time
35. READs and WRITEs with auto precharge are allowed to be issued before
36. When a single-bank PRECHARGE command is issued,
37. This parameter has a two clock minimum requirement at any
38. The
39. The minimum internal READ-to-PRECHARGE time. This is the time from which the last 4-
40.
41. The refresh period is 64ms (commercial) or 32ms (industrial and automotive). This equa-
42.
43.
44.
45. The half-clock of
strobe are listed in Table 33 (page 62)–Table 35 (page 63) on Table 33 (page 62),
Table 34 (page 63), and Table 35 (page 63); listed values are already derated for slew
rate variations and converted from baseline values to V
(page 53).
t
when the slew rate is 1 V/ns. The baseline values,
referenced from the logic trip points.
and V
V
the baseline values must be derated by adding the values from Table 28 (page 56) and
Table 29 (page 57).
due to
satisfied because
plies when the PRECHARGE (ALL) command is issued, regardless of the number of banks
open. For 8-bank devices (≥1Gb),
lists
ACTIVATE commands may be issued in a given
still applies.
bit prefetch begins to when the PRECHARGE command can be issued. A 4-bit prefetch is
when the READ command internally latches the READ so that data will output CL later.
This parameter is only applicable when
533 MHz when
(MIN) has to be satisfied as well. The DDR2 SDRAM will automatically delay the internal
PRECHARGE command until
t
ded up to the next integer.
t
programmed to four clocks would have
8 clocks.
tes to an average refresh rate of 7.8125µs (commercial) or 3.9607µs (industrial and
automotive). To ensure all rows of all banks are properly refreshed, 8192 REFRESH com-
mands must be issued every 64ms (commercial) or 32ms (industrial and automotive). The
JEDEC
allowed.
t
or to CK, CK# being removed in a system RESET condition (see Reset (page 123)).
t
Figure 68 (page 114).
t
clock edges. CKE must remain at the valid input level the entire time it takes to achieve
the three clocks of registration. Thus, after any CKE transition, CKE may not transition
from its valid level during the time period of
must be derated by the amount of half-clock duty cycle error. For example, if the clock
IH
DAL = (nWR) + (
WR parameter stored in the MR9–MR11. For example, -37E at
DELAY is calculated from
ISXR is equal to
CKE (MIN) of three clocks means CKE must be registered on three consecutive positive
IL
IH(DC)
/V
a
values (for reference only) are equivalent to the baseline values of
t
t
IH
RP [MIN] +
FAW (MIN) parameter applies to all 8-bank DDR2 devices. No more than four bank-
IL(AC)
t
DDR2 overshoot/undershoot. See AC Overshoot/Undershoot Specification
for a falling signal. If the command/address slew rate is not equal to 1 V/ns, then
t
RFC MAX of 70,000ns is not required as bursting of AUTO REFRESH commands is
WR during auto precharge.
for a falling signal, while
t
t
RTP = 7.5ns. If
t
CK [AVG] MIN).
t
RP/
IS and is used for CKE setup time during self refresh exit, as shown in
t
t
AOFD’s 2.5
RAS lockout feature is supported in DDR2 SDRAM.
t
CK). Each of these terms, if not already an integer, should be roun-
40
t
IS +
t
CK refers to the application clock period; nWR refers to the
t
RAS (MIN) has been satisfied.
t
CK assumes a 50/50 clock duty cycle. This half-clock value
t
t
RTP/(2 ×
CK +
t
RPA (MIN) =
Micron Technology, Inc. reserves the right to change products or specifications without notice.
t
t
IH
IH so that CKE registration LOW is guaranteed pri-
t
IS
b
t
b
t
t
RTP/(2 ×
CK) ≤ 1, then equation AL + BL/2 applies.
DAL = 4 + (15ns/3.75ns) clocks = 4 + (4) clocks =
is referenced from V
is referenced from V
1Gb: x4, x8, x16 DDR2 SDRAM
t
IS + 2 ×
t
t
RP (MIN) +
FAW (MIN) period.
t
t
CK) > 1, such as frequencies faster than
IS
b
,
t
RP timing applies.
t
t
CK +
IH
REF
b
t
, are the JEDEC-defined values,
IS
t
values.
CK (AVG) (Table 11 (page 31)
t
a
IH.
,
© 2004 Micron Technology, Inc. All rights reserved.
IL(DC)
t
t
IH(AC)
CK.
IH
t
CK = 3.75ns with
a
and
for a rising signal and
t
for a rising signal
RRD (MIN) restriction
t
IS
t
IS
t
b
t
RPA timing ap-
RAS (MIN) is
b
,
,
t
IH
t
IH
b
b
. The
at V
t
WR
t
RAS
t
REF
IS
a
,