MT47H128M8HQ-3 L:G Micron Technology Inc, MT47H128M8HQ-3 L:G Datasheet - Page 54

• Manufacturer Part Number: MT47H128M8HQ-3 L:G
• Description: IC DDR2 SDRAM 1GBIT 3NS 60FBGA
• Manufacturer: Micron Technology Inc
• Type: DDR2 SDRAMr

Specifications of MT47H128M8HQ-3 L:G

• Format - Memory: RAM
• Memory Type: DDR2 SDRAM
• Memory Size: 1G (128M x 8)
• Speed: 3ns
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 60-FBGA
• Organization: 128Mx8
• Density: 1Gb
• Address Bus: 17b
• Access Time (max): 450ps
• Maximum Clock Rate: 667MHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: FBGA
• Operating Temp Range: 0C to 85C
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 135mA
• Pin Count: 60
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 27: AC Input Test Conditions
PDF: 09005aef821ae8bf
1GbDDR2.pdf – Rev. T 02/10 EN
Parameter
Input setup timing measurement reference level address
balls, bank address balls, CS#, RAS#, CAS#, WE#, ODT,
DM, UDM, LDM, and CKE
Input hold timing measurement reference level address
balls, bank address balls, CS#, RAS#, CAS#, WE#, ODT,
DM, UDM, LDM, and CKE
Input timing measurement reference level (single-ended)
DQS for x4, x8; UDQS, LDQS for x16
Input timing measurement reference level (differential)
CK, CK# for x4, x8, x16; DQS, DQS# for x4, x8; RDQS,
RDQS# for x8; UDQS, UDQS#, LDQS, LDQS# for x16
Notes:
1. All voltages referenced to V
2. Input waveform setup timing (
3. See Input Slew Rate Derating (page 55).
4. The slew rate for single-ended inputs is measured from DC level to AC level, V
5. Input waveform hold (
6. Input waveform setup timing (
7. Input waveform setup timing (
8. Input waveform timing is referenced to the crossing point level (V
9. The slew rate for differentially ended inputs is measured from twice the DC level to
V
test, as shown in Figure 31 (page 66).
V
to V
Figure 24 (page 58), Figure 26 (page 59), Figure 28 (page 64), and Figure 30
(page 65).
V
test, as shown in Figure 31 (page 66).
referenced from the crossing of DQS, UDQS, or LDQS through the Vref level applied to
the device under test, as shown in Figure 33 (page 67).
is enabled is referenced from the cross-point of DQS/DQS#, UDQS/UDQS#, or LDQS/
LDQS#, as shown in Figure 32 (page 66).
(V
is the complementary input signal, as shown in Figure 34 (page 67).
twice the AC level: 2 × V
V
CK rising edge and would be +250mV to –500mV for CK falling edge.
IH(AC)
IH(AC)
IL(DC)
IH(DC)
TR
REF
and V
level for a rising signal and V
level for a rising signal and V
on the rising edge and V
, the valid intersection is where the “tangent” line intersects V
on the falling edge. For example, the CK/CK# would be –250mV to +500mV for
CP
) applied to the device under test, where V
t
IH
IL(DC)
b
54
Symbol
) timing is referenced from the input signal crossing at the
V
SS
REF(DC)
V
V
V
to 2 × V
.
AC Overshoot/Undershoot Specification
RH
RD
RS
t
t
t
IS
DS) and hold timing (
DS) and hold timing (
IL(AC)
b
) is referenced from the input signal crossing at the
IH(DC)
IL(AC)
Micron Technology, Inc. reserves the right to change products or specifications without notice.
to V
IH(AC)
V
DDQ
IH(DC)
for a falling signal applied to the device under
for a falling signal applied to the device under
Min
on the rising edge and 2 × V
× 0.49 V
1Gb: x4, x8, x16 DDR2 SDRAM
See Note 2
See Note 5
on the falling edge. For signals referenced
V
IX(AC)
DDQ
t
t
DH) for single-ended data strobe is
DH) when differential data strobe
Max
TR
× 0.51
is the true input signal and V
© 2004 Micron Technology, Inc. All rights reserved.
IX
Units
) of two input signals
V
V
REF
IL(AC)
, as shown in
to 2 ×
1, 3, 7, 8, 9
IL(DC)
1, 2, 3, 4
1, 3, 4, 5
1, 3, 4, 6
Notes
to
CP