MT47H128M8HQ-3 L:G Micron Technology Inc, MT47H128M8HQ-3 L:G Datasheet - Page 28

• Manufacturer Part Number: MT47H128M8HQ-3 L:G
• Description: IC DDR2 SDRAM 1GBIT 3NS 60FBGA
• Manufacturer: Micron Technology Inc
• Type: DDR2 SDRAMr

Specifications of MT47H128M8HQ-3 L:G

• Format - Memory: RAM
• Memory Type: DDR2 SDRAM
• Memory Size: 1G (128M x 8)
• Speed: 3ns
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 60-FBGA
• Organization: 128Mx8
• Density: 1Gb
• Address Bus: 17b
• Access Time (max): 450ps
• Maximum Clock Rate: 667MHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: FBGA
• Operating Temp Range: 0C to 85C
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 135mA
• Pin Count: 60
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 10: DDR2 I
Notes: 1–7 apply to the entire table
PDF: 09005aef821ae8bf
1GbDDR2.pdf – Rev. T 02/10 EN
Parameter/Condition
Operating one bank active-
precharge current:
t
=
HIGH between valid commands; Ad-
dress bus inputs are switching; Data
bus inputs are switching
Operating one bank active-read-
precharge current: I
= 4, CL = CL (I
(I
MIN (I
HIGH, CS# is HIGH between valid
commands; Address bus inputs are
switching; Data pattern is same as
I
Precharge power-down current:
All banks idle;
is LOW; Other control and address
bus inputs are stable; Data bus in-
puts are floating
Precharge quiet standby
current: All banks idle;
t
HIGH; Other control and address
bus inputs are stable; Data bus in-
puts are floating
Precharge standby current: All
banks idle;
HIGH, CS# is HIGH; Other control
and address bus inputs are switch-
ing; Data bus inputs are switching
Active power-down current: All
banks open;
LOW; Other control and address
bus inputs are stable; Data bus in-
puts are floating
Active standby current: All banks
open;
MAX (I
HIGH, CS# is HIGH between valid
commands; Other control and ad-
dress bus inputs are switching; Data
bus inputs are switching
CK =
DD4W
CK =
DD
t
RAS MIN (I
),
t
t
t
DD
RC =
t
CK (I
CK (I
DD
CK =
),
),
t
RCD =
DD
DD
t
t
t
RP =
RC (I
CK =
t
t
CK (I
DD
DD
CK =
),
); CKE is HIGH, CS# is
t
CK =
t
); CKE is HIGH, CS# is
), AL = 0;
RC =
DD
t
t
DD
RP (I
t
CK (I
RCD (I
t
),
CK (I
DD
),
t
t
t
CK (I
RAS =
RC (I
t
DD
OUT
RAS =
DD
Specifications and Conditions (Die Revisions E, G, and H)
DD
); CKE is
DD
); CKE is
t
= 0mA; BL
CK =
DD
DD
); CKE is
); CKE is
t
); CKE
RAS
),
t
RAS
t
t
RAS
CK
Symbol
I
I
I
I
I
I
DD3Pf
DD3Ps
I
I
DD2Q
DD2N
DD3N
DD2P
DD0
DD1
Configuration
x4, x8, x16
MR12 = 0
MR12 = 1
Slow exit
Fast exit
x4, x8
x4, x8
x4, x8
x4, x8
x4, x8
x16
x16
x16
x16
x16
28
Electrical Specifications – I
-187E
115
180
130
210
60
90
60
95
50
10
70
95
7
Micron Technology, Inc. reserves the right to change products or specifications without notice.
-25E/
150
110
175
-25
90
50
75
50
80
40
10
60
85
7
1Gb: x4, x8, x16 DDR2 SDRAM
-3E/
135
100
130
85
40
65
40
70
30
10
55
75
-3
7
© 2004 Micron Technology, Inc. All rights reserved.
-37E
110
120
70
95
40
45
40
50
30
10
45
60
7
DD
110
115
-5E
70
90
35
40
35
40
30
10
40
55
Parameters
7
Units
mA
mA
mA
mA
mA
mA
mA