MT47H128M8HQ-3 L:G Micron Technology Inc, MT47H128M8HQ-3 L:G Datasheet - Page 72

• Manufacturer Part Number: MT47H128M8HQ-3 L:G
• Description: IC DDR2 SDRAM 1GBIT 3NS 60FBGA
• Manufacturer: Micron Technology Inc
• Type: DDR2 SDRAMr

Specifications of MT47H128M8HQ-3 L:G

• Format - Memory: RAM
• Memory Type: DDR2 SDRAM
• Memory Size: 1G (128M x 8)
• Speed: 3ns
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 60-FBGA
• Organization: 128Mx8
• Density: 1Gb
• Address Bus: 17b
• Access Time (max): 450ps
• Maximum Clock Rate: 667MHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: FBGA
• Operating Temp Range: 0C to 85C
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 135mA
• Pin Count: 60
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 39: Minimum Delay with Auto Precharge Enabled
DESELECT
PDF: 09005aef821ae8bf
1GbDDR2.pdf – Rev. T 02/10 EN
From Command (Bank n)
WRITE with auto precharge
READ with auto precharge
The DESELECT function (CS# HIGH) prevents new commands from being executed by
the DDR2 SDRAM. The DDR2 SDRAM is effectively deselected. Operations already in
progress are not affected. DESELECT is also referred to as COMMAND INHIBIT.
10. The number of clock cycles required to meet
4. REFRESH and LOAD MODE commands may only be issued when all banks are idle.
5. Not used.
6. All states and sequences not shown are illegal or reserved.
7. READs or WRITEs listed in the Command/Action column include READs or WRITEs with
8. A WRITE command may be applied after the completion of the READ burst.
9. Requires appropriate DM.
WRITE or WRITE with auto precharge
WRITE or WRITE with auto precharge
auto precharge enabled and READs or WRITEs with auto precharge disabled.
is greater.
READ or READ with auto precharge
READ or READ with auto precharge
READ with auto
precharge enabled/
WRITE with auto
precharge enabled:
The minimum delay from a READ or WRITE command with auto precharge enabled to
a command to a different bank is summarized in Table 39 (page 72).
PRECHARGE or ACTIVATE
PRECHARGE or ACTIVATE
To Command (Bank m)
The READ with auto precharge enabled or WRITE with auto pre-
charge enabled states can each be broken into two parts: the
access period and the precharge period. For READ with auto pre-
charge, the precharge period is defined as if the same burst was
executed with auto precharge disabled and then followed with
the earliest possible PRECHARGE command that still accesses all
of the data in the burst. For WRITE with auto precharge, the pre-
charge period begins when
auto precharge was disabled. The access period starts with regis-
tration of the command and ends where the precharge period
(or
such that when a READ with auto precharge is enabled or a
WRITE with auto precharge is enabled, any command to other
banks is allowed, as long as that command does not interrupt
the read or write data transfer already in process. In either case,
all other related limitations apply (contention between read da-
ta and write data must be avoided).
72
t
RP) begins. This device supports concurrent auto precharge
Micron Technology, Inc. reserves the right to change products or specifications without notice.
(with Concurrent Auto Precharge)
1Gb: x4, x8, x16 DDR2 SDRAM
t
WTR is either two or
(CL - 1) + (BL/2) +
t
Minimum Delay
WR ends, with
(BL/2) + 2
(BL/2)
(BL/2)
1
1
© 2004 Micron Technology, Inc. All rights reserved.
t
t
t
WTR
WR measured as if
WTR/
Commands
t
CK, whichever
Units
t
t
t
t
t
t
CK
CK
CK
CK
CK
CK