MT47H128M8HQ-3 L:G Micron Technology Inc, MT47H128M8HQ-3 L:G Datasheet - Page 88

• Manufacturer Part Number: MT47H128M8HQ-3 L:G
• Description: IC DDR2 SDRAM 1GBIT 3NS 60FBGA
• Manufacturer: Micron Technology Inc
• Type: DDR2 SDRAMr

Specifications of MT47H128M8HQ-3 L:G

• Format - Memory: RAM
• Memory Type: DDR2 SDRAM
• Memory Size: 1G (128M x 8)
• Speed: 3ns
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 60-FBGA
• Organization: 128Mx8
• Density: 1Gb
• Address Bus: 17b
• Access Time (max): 450ps
• Maximum Clock Rate: 667MHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: FBGA
• Operating Temp Range: 0C to 85C
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 135mA
• Pin Count: 60
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ACTIVATE
Figure 43: Example: Meeting
PDF: 09005aef821ae8bf
1GbDDR2.pdf – Rev. T 02/10 EN
Bank address
Command
Address
CK#
CK
Bank x
ACT
Row
T0
NOP
T1
Before any READ or WRITE commands can be issued to a bank within the DDR2
SDRAM, a row in that bank must be opened (activated), even when additive latency is
used. This is accomplished via the ACTIVATE command, which selects both the bank
and the row to be activated.
After a row is opened with an ACTIVATE command, a READ or WRITE command may
be issued to that row subject to the
by the clock period and rounded up to the next whole number to determine the earliest
clock edge after the ACTIVATE command on which a READ or WRITE command can be
entered. The same procedure is used to convert other specification limits from time
units to clock cycles. For example, a
clock (
which covers any case where 5 <
t
A subsequent ACTIVATE command to a different row in the same bank can only be is-
sued after the previous active row has been closed (precharged). The minimum time
interval between successive ACTIVATE commands to the same bank is defined by
A subsequent ACTIVATE command to another bank can be issued while the first bank is
being accessed, which results in a reduction of total row-access overhead. The mini-
mum time interval between successive ACTIVATE commands to different banks is
defined by
DDR2 devices with 8 banks (1Gb or larger) have an additional requirement:
requires no more than four ACTIVATE commands may be issued in any given
(MIN) period, as shown in Figure 44 (page 89).
RRD where 2 <
t RRD
t
t
CK = 3.75ns) results in 5.3 clocks, rounded up to 6. This is shown in Figure 43,
RRD (MIN) and
NOP
T2
t
RRD.
t
RRD (MIN)/
Bank y
ACT
Row
T3
t
RCD (MIN)
NOP
t
T4
CK ≤ 3.
88
t RRD
t
t RCD
RCD (MIN)/
t
RCD specification.
t
RCD (MIN) specification of 20ns with a 266 MHz
NOP
T5
Micron Technology, Inc. reserves the right to change products or specifications without notice.
t
CK ≤ 6. Figure 43 also shows the case for
1Gb: x4, x8, x16 DDR2 SDRAM
Bank z
NOP
Row
T6
t
RCD (MIN) should be divided
NOP
T7
© 2004 Micron Technology, Inc. All rights reserved.
NOP
T8
ACTIVATE
t
FAW. This
RD/WR
Bank y
Col
Don’t Care
T9
t
FAW
t
RC.