MT47H128M8HQ-3 L:G Micron Technology Inc, MT47H128M8HQ-3 L:G Datasheet - Page 98

• Manufacturer Part Number: MT47H128M8HQ-3 L:G
• Description: IC DDR2 SDRAM 1GBIT 3NS 60FBGA
• Manufacturer: Micron Technology Inc
• Type: DDR2 SDRAMr

Specifications of MT47H128M8HQ-3 L:G

• Format - Memory: RAM
• Memory Type: DDR2 SDRAM
• Memory Size: 1G (128M x 8)
• Speed: 3ns
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 60-FBGA
• Organization: 128Mx8
• Density: 1Gb
• Address Bus: 17b
• Access Time (max): 450ps
• Maximum Clock Rate: 667MHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: FBGA
• Operating Temp Range: 0C to 85C
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 135mA
• Pin Count: 60
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 53: Bank Read – with Auto Precharge
PDF: 09005aef821ae8bf
1GbDDR2.pdf – Rev. T 02/10 EN
Bank address
Command 1
DQS, DQS#
DQS, DQS#
Case 2: t AC (MAX) and t DQSCK (MAX)
Case 1: t AC (MIN) and t DQSCK (MIN)
Address
DQ 6
DQ 6
CK#
CKE
A10
DM
CK
NOP 1
T0
Notes:
Bank x
ACT
RA
RA
T1
1. NOP commands are shown for ease of illustration; other commands may be valid at
2. BL = 4, RL = 4 (AL = 1, CL = 3) in the case shown.
3. The DDR2 SDRAM internally delays auto precharge until both
4. Enable auto precharge.
5. I/O balls, when entering or exiting High-Z, are not referenced to a specific voltage level,
6. DO n = data-out from column n; subsequent elements are applied in the programmed
t CK
these times.
have been satisfied.
but to when the device begins to drive or no longer drives, respectively.
order.
t RCD
t RAS
t RC
NOP 1
T2
t CH
t CL
READ 2,3
Bank x
Col n
4
T3
AL = 1
prefetch
4-bit
NOP 1
98
T4
t RTP
NOP 1
Micron Technology, Inc. reserves the right to change products or specifications without notice.
T5
t LZ (MIN)
t LZ (MAX)
CL = 3
Internal
precharge
1Gb: x4, x8, x16 DDR2 SDRAM
5
NOP 1
T6
5
t RPRE
t LZ (MIN)
t LZ (MAX)
t RPRE
NOP 1
Transitioning Data
T7
t DQSCK (MIN)
t RP
DO
t DQSCK (MAX)
t AC (MIN)
n
t AC (MAX)
DO
© 2004 Micron Technology, Inc. All rights reserved.
n
T7n
t
RAS (MIN) and
NOP 1
T8
t HZ (MIN)
t HZ (MAX)
T8n
t RPST
t RPST
Don’t Care
Bank x
ACT
RA
5
RA
t
RTP (MIN)
5
READ