MT47H128M8HQ-3 L:G Micron Technology Inc, MT47H128M8HQ-3 L:G Datasheet - Page 97

• Manufacturer Part Number: MT47H128M8HQ-3 L:G
• Description: IC DDR2 SDRAM 1GBIT 3NS 60FBGA
• Manufacturer: Micron Technology Inc
• Type: DDR2 SDRAMr

Specifications of MT47H128M8HQ-3 L:G

• Format - Memory: RAM
• Memory Type: DDR2 SDRAM
• Memory Size: 1G (128M x 8)
• Speed: 3ns
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 60-FBGA
• Organization: 128Mx8
• Density: 1Gb
• Address Bus: 17b
• Access Time (max): 450ps
• Maximum Clock Rate: 667MHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: FBGA
• Operating Temp Range: 0C to 85C
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 135mA
• Pin Count: 60
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 52: Bank Read – Without Auto Precharge
PDF: 09005aef821ae8bf
1GbDDR2.pdf – Rev. T 02/10 EN
Bank address
Case 1: t AC (MIN) and t DQSCK (MIN)
DQS, DQS#
DQS, DQS#
Command
Case 2: t AC (MAX) and t DQSCK (MAX)
Address
DQ 8
DQ 8
CK#
CKE
A10
DM
CK
NOP 1
T0
Notes:
Bank x
ACT
RA
RA
T1
1. NOP commands are shown for ease of illustration; other commands may be valid at
2. BL = 4 and AL = 0 in the case shown.
3. The PRECHARGE command can only be applied at T6 if
4. READ-to-PRECHARGE = AL + BL/2 - 2CK + MAX (
5. Disable auto precharge.
6. “Don’t Care” if A10 is HIGH at T5.
7. I/O balls, when entering or exiting High-Z, are not referenced to a specific voltage level,
8. DO n = data-out from column n; subsequent elements are applied in the programmed
these times.
but to when the device begins to drive or no longer drives, respectively.
order.
t CK
t RAS 3
t RCD
t RC
NOP 1
T2
t CH
t CL
NOP 1
T3
Bank x
READ 2
5
Col n
97
T4
CL = 3
t RTP 4
NOP 1
T5
Micron Technology, Inc. reserves the right to change products or specifications without notice.
t LZ (MIN)
t LZ (MAX)
One bank
All banks
1Gb: x4, x8, x16 DDR2 SDRAM
Bank x 6
7
PRE 3
T6
7
t
t RPRE
RTP/
t LZ (MIN)
t LZ (MIN)
t RPRE
t
Transitioning Data
CK or 2CK).
t
NOP 1
RAS (MIN) is met.
T7
t DQSCK (MAX)
t DQSCK (MIN)
t RP
DO
n
t AC (MIN)
t AC (MAX)
DO
© 2004 Micron Technology, Inc. All rights reserved.
n
T7n
NOP 1
T8
t HZ (MIN)
t HZ (MAX)
T8n
t RPST
Don’t Care
t RPST
Bank x
ACT
RA
T9
7
RA
7
READ