MT47H128M8HQ-3 L:G Micron Technology Inc, MT47H128M8HQ-3 L:G Datasheet - Page 71

• Manufacturer Part Number: MT47H128M8HQ-3 L:G
• Description: IC DDR2 SDRAM 1GBIT 3NS 60FBGA
• Manufacturer: Micron Technology Inc
• Type: DDR2 SDRAMr

Specifications of MT47H128M8HQ-3 L:G

• Format - Memory: RAM
• Memory Type: DDR2 SDRAM
• Memory Size: 1G (128M x 8)
• Speed: 3ns
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 60-FBGA
• Organization: 128Mx8
• Density: 1Gb
• Address Bus: 17b
• Access Time (max): 450ps
• Maximum Clock Rate: 667MHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: FBGA
• Operating Temp Range: 0C to 85C
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 135mA
• Pin Count: 60
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 38: Truth Table – Current State Bank n – Command to Bank m
Notes: 1–6 apply to the entire table
PDF: 09005aef821ae8bf
1GbDDR2.pdf – Rev. T 02/10 EN
Current State
Any
Idle
Row
active, active,
or precharge
Read (auto
precharge
disabled)
Write (auto pre-
charge
disabled)
Read (with
auto
precharge)
Write (with
auto
precharge)
CS#
H
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
Notes:
RAS#
X
H
X
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
1. This table applies when CKEn - 1 was HIGH and CKEn is HIGH and after
2. This table describes an alternate bank operation, except where noted (the current state
3. Current state definitions:
met (if the previous state was self refresh).
is for bank n and the commands shown are those allowed to be issued to bank m, assum-
ing that bank m is in such a state that the given command is allowable). Exceptions are
covered in the notes below.
Idle:
Row active:
Read:
Write:
CAS#
X
H
X
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
WE#
H
H
H
H
H
H
H
H
H
H
H
X
X
L
L
L
L
L
L
L
L
L
L
DESELECT (NOP/continue previous operation)
NO OPERATION (NOP/continue previous operation)
Any command otherwise allowed to bank m
ACTIVATE (select and activate row)
READ (select column and start READ burst)
WRITE (select column and start WRITE burst)
PRECHARGE
ACTIVATE (select and activate row)
READ (select column and start new READ burst)
WRITE (select column and start WRITE burst)
PRECHARGE
ACTIVATE (select and activate row)
READ (select column and start READ burst)
WRITE (select column and start new WRITE burst)
PRECHARGE
ACTIVATE (select and activate row)
READ (select column and start new READ burst)
WRITE (select column and start WRITE burst)
PRECHARGE
ACTIVATE (select and activate row)
READ (select column and start READ burst)
WRITE (select column and start new WRITE burst)
PRECHARGE
The bank has been precharged,
burst is complete.
A row in the bank has been activated and
No data bursts/accesses and no register accesses are in progress.
A READ burst has been initiated with auto precharge disabled
and has not yet terminated.
A WRITE burst has been initiated with auto precharge disabled
and has not yet terminated.
71
Micron Technology, Inc. reserves the right to change products or specifications without notice.
Command/Action
1Gb: x4, x8, x16 DDR2 SDRAM
t
RP has been met, and any READ
© 2004 Micron Technology, Inc. All rights reserved.
t
RCD has been met.
t
XSNR has been
Commands
7, 9, 10
Notes
7, 10
7, 8
7, 8
7
7
7
7
7
7