MT47H128M8HQ-3 L:G Micron Technology Inc, MT47H128M8HQ-3 L:G Datasheet - Page 123

• Manufacturer Part Number: MT47H128M8HQ-3 L:G
• Description: IC DDR2 SDRAM 1GBIT 3NS 60FBGA
• Manufacturer: Micron Technology Inc
• Type: DDR2 SDRAMr

Specifications of MT47H128M8HQ-3 L:G

• Format - Memory: RAM
• Memory Type: DDR2 SDRAM
• Memory Size: 1G (128M x 8)
• Speed: 3ns
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 60-FBGA
• Organization: 128Mx8
• Density: 1Gb
• Address Bus: 17b
• Access Time (max): 450ps
• Maximum Clock Rate: 667MHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: FBGA
• Operating Temp Range: 0C to 85C
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 135mA
• Pin Count: 60
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Reset
CKE Low Anytime
PDF: 09005aef821ae8bf
1GbDDR2.pdf – Rev. T 02/10 EN
DDR2 SDRAM applications may go into a reset state anytime during normal operation.
If an application enters a reset condition, CKE is used to ensure the DDR2 SDRAM de-
vice resumes normal operation after reinitializing. All data will be lost during a reset
condition; however, the DDR2 SDRAM device will continue to operate properly if the
following conditions outlined in this section are satisfied.
The reset condition defined here assumes all supply voltages (V
V
eration. All other input balls of the DDR2 SDRAM device are a “Don’t Care” during
RESET with the exception of CKE.
If CKE asynchronously drops LOW during any valid operation (including a READ or
WRITE burst), the memory controller must satisfy the timing parameter
turning off the clocks. Stable clocks must exist at the CK, CK# inputs of the DRAM be-
fore CKE is raised HIGH, at which time the normal initialization sequence must occur
(see Initialization). The DDR2 SDRAM device is now ready for normal operation after
the initialization sequence. Figure 79 (page 124) shows the proper sequence for a RE-
SET operation.
REF
3. Minimum CKE high time is
4. If this command is a PRECHARGE (or if the device is already in the idle state), then the
) are stable and meet all DC specifications prior to, during, and after the RESET op-
This requires a minimum of three clock cycles of registration.
power-down mode shown is precharge power-down, which is required prior to the
clock frequency change.
123
t
CKE = 3 ×
Micron Technology, Inc. reserves the right to change products or specifications without notice.
t
CK. Minimum CKE LOW time is
1Gb: x4, x8, x16 DDR2 SDRAM
© 2004 Micron Technology, Inc. All rights reserved.
DD
, V
DDQ
t
CKE = 3 ×
t
, V
DELAY before
DDL
, and
Reset
t
CK.