MT47H128M8HQ-3 L:G Micron Technology Inc, MT47H128M8HQ-3 L:G Datasheet - Page 119

IC DDR2 SDRAM 1GBIT 3NS 60FBGA

MT47H128M8HQ-3 L:G

Manufacturer Part Number
MT47H128M8HQ-3 L:G
Description
IC DDR2 SDRAM 1GBIT 3NS 60FBGA
Manufacturer
Micron Technology Inc
Type
DDR2 SDRAMr

Specifications of MT47H128M8HQ-3 L:G

Format - Memory
RAM
Memory Type
DDR2 SDRAM
Memory Size
1G (128M x 8)
Speed
3ns
Interface
Parallel
Voltage - Supply
1.7 V ~ 1.9 V
Operating Temperature
0°C ~ 85°C
Package / Case
60-FBGA
Organization
128Mx8
Density
1Gb
Address Bus
17b
Access Time (max)
450ps
Maximum Clock Rate
667MHz
Operating Supply Voltage (typ)
1.8V
Package Type
FBGA
Operating Temp Range
0C to 85C
Operating Supply Voltage (max)
1.9V
Operating Supply Voltage (min)
1.7V
Supply Current
135mA
Pin Count
60
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Figure 72: WRITE-to-Power-Down or Self Refresh Entry
Figure 73: WRITE with Auto Precharge-to-Power-Down or Self Refresh Entry
PDF: 09005aef821ae8bf
1GbDDR2.pdf – Rev. T 02/10 EN
DQS, DQS#
DQS, DQS#
Command
Command
Address
Address
CK#
CKE
A10
CK#
CKE
A10
DQ
DQ
CK
CK
WRITE
Valid
Valid
WRITE
T0
T0
Notes:
Note:
NOP
NOP
T1
T1
WL = 3
WL = 3
1. Power-down or self refresh entry may occur after the WRITE burst completes.
1. Internal PRECHARGE occurs at Ta0 when WR has completed; power-down entry may oc-
2. WR is programmed through MR9–MR11 and represents (
cur 1 x
to next integer
NOP
NOP
T2
T2
t
CK later at Ta1, prior to
NOP
t
DO
NOP
DO
CK.
T3
T3
DO
DO
119
Valid
Valid
DO
DO
T4
T4
t
RP being satisfied.
DO
DO
Indicates a break in
time scale
Micron Technology, Inc. reserves the right to change products or specifications without notice.
Valid
Valid
T5
T5
1Gb: x4, x8, x16 DDR2 SDRAM
WR 2
Valid 1
Valid
t WTR
Ta0
T6
Transitioning Data
t
self refresh entry 1
self refresh entry
Power-down or
WR [MIN] ns/
Power-down or
Transitioning Data
Power-Down Mode
© 2004 Micron Technology, Inc. All rights reserved.
NOP 1
NOP
Ta1
T7
t
CK) rounded up
t CKE (MIN)
t CKE (MIN)
Ta2
T8
Don’t Care
Don’t Care

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