L6711TR STMicroelectronics, L6711TR Datasheet - Page 45

• Manufacturer Part Number: L6711TR
• Description: IC CTRLR 3PHASE VID/DACS 48-TQFP
• Manufacturer: STMicroelectronics
• Type: Step-Down (Buck)r

Specifications of L6711TR

• Internal Switch(s): No
• Synchronous Rectifier: No
• Number Of Outputs: 1
• Voltage - Output: 0.8 ~ 1.55 V
• Current - Output: 2A
• Frequency - Switching: 150kHz
• Voltage - Input: 12V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 48-TQFP Exposed Pad, 48-eTQFP, 48-HTQFP, 48-VQFP
• Power - Output: 2.5W
• Output Voltage: 0.8 V to 1.581 V
• Output Current: 95 A
• Input Voltage: 13.8 V
• Mounting Style: SMD/SMT
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-5363-2; L6711TR

L6711
18.2
Power connections related.
Figure 24 shows some small signal components placement.
Gate and phase traces must be sized according to the driver RMS current delivered to
the power mosfet. The device robustness allows managing applications with the power
section far from the controller without losing performances. Anyway, when possible, it is
suggested to minimize the distance between controller and power section.
In addition, since the PHASEx pin is the return path for the high side driver, this pin
might be connected directly to the High Side mosfet Source pin to have a proper driving
for this mosfet. For the LS mosfets, the return path is the PGNDx pin: it can be
connected directly to the power ground plane.
Bootstrap capacitor must be placed as close as possible to the BOOTx and PHASEx
pins to minimize the loop that is created.
Decoupling capacitor from VCC and SGND placed as close as possible to the involved
pins.
Decoupling capacitor from VCCDRx and PGNDx placed as close as possible to those
pins. This capacitor sustains the peak currents requested by the low-side mosfet
drivers.
Sensible components must be referred to SGND (when present): frequency set-up
resistor R
Star grounding: Connect SGND to PGND plane in a single point to avoid that drops due
to the high current delivered causes errors in the device behavior.
An additional ceramic capacitor is suggested to place near HS mosfet drain. This helps
in reducing HF noise.
VSEN pin filtered vs. SGND helps in reducing noise injection into device.
OUTEN pin filtered vs. SGND helps in reducing false trip due to coupled noise: take
care in routing driving net for this pin in order to minimize coupled noise.
PHASE pin spikes. Since the HS mosfet switches hardly, heavy voltage spikes can be
observed on the PHASEx pins. If these voltage spikes overcome the max breakdown
voltage of the pin, the device can absorb energy and it can cause damages. The
voltage spikes must be limited by proper layout; by the use of gate resistors, Schottky
diodes in parallel to the low side mosfets and/or snubber network on the low side
mosfets, and cannot overcome 26V, for 20nSec, at F
Boot Capacitor Extra Charge. Systems that do not use Schottky diodes might show big
negative spikes on the phase pin. This spike can be limited as well as the positive spike
but has an additional consequence: it causes the bootstrap capacitor to be over-
charged. This extra-charge can cause, in the worst case condition of maximum input
voltage and during particular transients, that boot-to-phase voltage overcomes the abs.
max. ratings also causing device failures. It is then suggested in this cases to limit this
extra-charge by adding a small resistor in series to the boot diode (one resistor can be
enough for all the three diodes if placed upstream the diode anode, see
OSC
, offset resistor R
OFFSET
, TC resistor R
TC
SW
and OVP resistor R
= 600kHz.
Layout guidelines
Figure
OVP
.
23).
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