C8051F410DK Silicon Laboratories Inc, C8051F410DK Datasheet - Page 101

• Manufacturer Part Number: C8051F410DK
• Description: KIT DEV FOR C8051F41X
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F410DK

• Contents: Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
• Processor To Be Evaluated: C8051F41x
• Interface Type: USB
• Silicon Manufacturer: Silicon Labs
• Core Architecture: 8051
• Silicon Core Number: C8051F410
• Silicon Family Name: C8051F41x
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: Silicon Laboratories C8051F41x
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1314

10.3. Power Management Modes
The CIP-51 core has two software programmable power management modes: Idle and Stop. Idle mode
halts the CPU while leaving the peripherals and internal clocks active. In Stop mode, the CPU is halted, all
interrupts and timers (except the Missing Clock Detector) are inactive, and the internal oscillator is stopped
(analog peripherals remain in their selected states; the external oscillator is not affected). Since clocks are
running in Idle mode, power consumption is dependent upon the system clock frequency and the number
of peripherals left in active mode before entering Idle. Stop mode consumes the least power. SFR Defini-
tion 10.7 describes the Power Control Register (PCON) used to control the CIP-51's power management
modes.
Although the CIP-51 has Idle and Stop modes built in (as with any standard 8051 architecture), power
management of the entire MCU is better accomplished by enabling/disabling individual peripherals as
needed. Each analog peripheral can be disabled when not in use and placed in low power mode. Digital
peripherals, such as timers or serial buses, draw little power when they are not in use. Turning off the oscil-
lators lowers power consumption considerably; however a reset is required to restart the MCU.
The C8051F41x devices feature a low-power SUSPEND mode, which stops the internal oscillator until a
wakening event occurs. See Section “
Bits7–0: ACC: Accumulator.
Bits7–0: B: B Register.
ACC.7
R/W
R/W
B.7
Bit7
Bit7
This register is the accumulator for arithmetic operations.
This register serves as a second accumulator for certain arithmetic operations.
ACC.6
R/W
R/W
B.6
Bit6
Bit6
ACC.5
SFR Definition 10.5. ACC: Accumulator
R/W
R/W
B.5
Bit5
Bit5
SFR Definition 10.6. B: B Register
19.1.1. Internal Oscillator Suspend Mode
ACC.4
R/W
R/W
B.4
Bit4
Bit4
Rev. 1.1
ACC.3
R/W
R/W
B.3
Bit3
Bit3
ACC.2
R/W
R/W
B.2
Bit2
Bit2
C8051F410/1/2/3
ACC.1
R/W
R/W
B.1
Bit1
Bit1
” on page
SFR Address: 0xE0
SFR Address: 0xF0
ACC.0
R/W
R/W
B.0
Bit0
Bit0
166
00000000
Addressable
Reset Value
00000000
Addressable
Reset Value
.
Bit
Bit
101