LPC2929FBD144,551 NXP Semiconductors, LPC2929FBD144,551 Datasheet - Page 94

• Manufacturer Part Number: LPC2929FBD144,551
• Description: IC ARM9 MCU FLASH 768K 144LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC2900r

Specifications of LPC2929FBD144,551

• Program Memory Type: FLASH
• Program Memory Size: 768KB (768K x 8)
• Package / Case: 144-LQFP
• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 125MHz
• Connectivity: CAN, EBI/EMI, I²C, LIN, SPI, UART/USART, USB
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 104
• Eeprom Size: 16K x 8
• Ram Size: 56K x 8
• Voltage - Supply (vcc/vdd): 1.71 V ~ 3.6 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC29
• Core: ARM968E-S
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 56 KB
• Interface Type: CAN/UART/USB
• Maximum Clock Frequency: 125 MHz
• Number Of Programmable I/os: 104
• Number Of Timers: 6
• Operating Supply Voltage: 1.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2, MCB2929, MCB2929U, MCB2929UME
• Development Tools By Supplier: OM11026, OM11038
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 3 (8-ch x 10-bit)
• Package: 144LQFP
• Device Core: ARM968E-S
• Family Name: LPC2900
• Maximum Speed: 125 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 568-4786 - EXT BOARD MOTOR CONTROL LPC2900
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4695; 935287118551; LPC2929FBD144-S

NXP Semiconductors
18. Contents
1
2
3
3.1
4
5
5.1
5.2
5.2.1
5.2.2
6
6.1
6.2
6.3
6.4
6.5
6.6
6.6.1
6.6.2
6.6.3
6.6.3.1
6.6.4
6.7
6.7.1
6.7.2
6.8
6.8.1
6.8.2
6.8.3
6.8.4
6.8.5
6.8.6
6.9
6.9.1
6.9.2
6.9.3
6.9.4
6.10
6.10.1
6.10.2
6.11
6.11.1
6.11.2
6.11.3
6.11.4
6.12
LPC2926_27_29
Product data sheet
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 3
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pinning information . . . . . . . . . . . . . . . . . . . . . . 5
Functional description . . . . . . . . . . . . . . . . . . 11
Reset, debug, test, and power description . . . 15
Reset and power-up behavior . . . . . . . . . . . . 15
IEEE 1149.1 interface pins
(JTAG boundary scan test) . . . . . . . . . . . . . . . 15
Base clock and branch clock relationship. . . . 18
External memory timing diagrams . . . . . . . . . 24
General Purpose DMA (GPDMA) controller . . 26
General subsystem. . . . . . . . . . . . . . . . . . . . . 29
Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5
General description . . . . . . . . . . . . . . . . . . . . . 5
LQFP144 pin assignment . . . . . . . . . . . . . . . . . 5
Architectural overview . . . . . . . . . . . . . . . . . . 11
ARM968E-S processor . . . . . . . . . . . . . . . . . . 12
On-chip flash memory system . . . . . . . . . . . . 13
On-chip static RAM. . . . . . . . . . . . . . . . . . . . . 13
Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . 14
Reset strategy . . . . . . . . . . . . . . . . . . . . . . . . 15
ETM/ETB . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Power supply pins . . . . . . . . . . . . . . . . . . . . . 16
Clocking strategy . . . . . . . . . . . . . . . . . . . . . . 16
Clock architecture . . . . . . . . . . . . . . . . . . . . . . 16
Flash memory controller . . . . . . . . . . . . . . . . . 20
Functional description. . . . . . . . . . . . . . . . . . . 20
Pin description . . . . . . . . . . . . . . . . . . . . . . . . 21
Clock description . . . . . . . . . . . . . . . . . . . . . . 21
Flash layout . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Flash bridge wait-states . . . . . . . . . . . . . . . . . 22
EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
External static memory controller . . . . . . . . . . 23
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Pin description . . . . . . . . . . . . . . . . . . . . . . . . 24
Clock description . . . . . . . . . . . . . . . . . . . . . . 24
DMA support for peripherals. . . . . . . . . . . . . . 26
Clock description . . . . . . . . . . . . . . . . . . . . . . 27
USB interface . . . . . . . . . . . . . . . . . . . . . . . . . 27
USB device controller . . . . . . . . . . . . . . . . . . . 27
USB OTG controller . . . . . . . . . . . . . . . . . . . . 27
Pin description . . . . . . . . . . . . . . . . . . . . . . . . 28
Clock description . . . . . . . . . . . . . . . . . . . . . . 28
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 28 September 2010
6.12.1
6.12.2
6.12.3
6.12.4
6.12.4.1
6.13
6.13.1
6.13.2
6.13.2.1
6.13.2.2
6.13.3
6.13.3.1
6.13.3.2
6.13.4
6.13.4.1
6.13.4.2
6.13.5
6.13.5.1
6.13.5.2
6.13.5.3
6.13.6
6.13.6.1
6.13.6.2
6.13.6.3
6.14
6.14.1
6.14.1.1
6.14.1.2
6.14.2
6.14.2.1
6.14.3
6.14.3.1
6.15
6.15.1
6.15.2
6.15.3
6.15.4
6.15.4.1
6.15.4.2
6.15.4.3
6.15.5
6.15.5.1
6.15.5.2
6.15.5.3
6.15.5.4
6.15.5.5
6.15.6
6.15.6.1
ARM9 microcontroller with CAN, LIN, and USB
General subsystem clock description . . . . . . 29
Chip and feature identification . . . . . . . . . . . . 29
System Control Unit (SCU) . . . . . . . . . . . . . . 29
Event router . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Pin description . . . . . . . . . . . . . . . . . . . . . . . . 30
Peripheral subsystem . . . . . . . . . . . . . . . . . . 30
Peripheral subsystem clock description. . . . . 30
Watchdog timer . . . . . . . . . . . . . . . . . . . . . . . 30
Functional description . . . . . . . . . . . . . . . . . . 31
Clock description . . . . . . . . . . . . . . . . . . . . . . 31
Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Pin description . . . . . . . . . . . . . . . . . . . . . . . . 32
Clock description . . . . . . . . . . . . . . . . . . . . . . 32
UARTs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Pin description . . . . . . . . . . . . . . . . . . . . . . . . 33
Clock description . . . . . . . . . . . . . . . . . . . . . . 33
Serial Peripheral Interface (SPI) . . . . . . . . . . 33
Functional description . . . . . . . . . . . . . . . . . . 34
Pin description . . . . . . . . . . . . . . . . . . . . . . . . 34
Clock description . . . . . . . . . . . . . . . . . . . . . . 35
General-purpose I/O . . . . . . . . . . . . . . . . . . . 35
Functional description . . . . . . . . . . . . . . . . . . 35
Pin description . . . . . . . . . . . . . . . . . . . . . . . . 35
Clock description . . . . . . . . . . . . . . . . . . . . . . 36
Networking subsystem. . . . . . . . . . . . . . . . . . 36
CAN gateway . . . . . . . . . . . . . . . . . . . . . . . . . 36
Global acceptance filter . . . . . . . . . . . . . . . . . 36
Pin description . . . . . . . . . . . . . . . . . . . . . . . . 37
LIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Pin description . . . . . . . . . . . . . . . . . . . . . . . . 37
I
Pin description . . . . . . . . . . . . . . . . . . . . . . . . 38
Modulation and sampling control subsystem . 38
Functional description . . . . . . . . . . . . . . . . . . 38
Pin description . . . . . . . . . . . . . . . . . . . . . . . . 41
Clock description . . . . . . . . . . . . . . . . . . . . . . 41
Analog-to-digital converter . . . . . . . . . . . . . . . 41
Functional description . . . . . . . . . . . . . . . . . . 42
Pin description . . . . . . . . . . . . . . . . . . . . . . . . 42
Clock description . . . . . . . . . . . . . . . . . . . . . . 43
Pulse Width Modulator (PWM). . . . . . . . . . . . 44
Functional description . . . . . . . . . . . . . . . . . . 44
Synchronizing the PWM counters . . . . . . . . . 45
Master and slave mode . . . . . . . . . . . . . . . . . 46
Pin description . . . . . . . . . . . . . . . . . . . . . . . . 46
Clock description . . . . . . . . . . . . . . . . . . . . . . 46
Timers in the MSCSS. . . . . . . . . . . . . . . . . . . 46
Pin description . . . . . . . . . . . . . . . . . . . . . . . . 47
2
C-bus serial I/O controllers . . . . . . . . . . . . . 37
LPC2926/2927/2929
© NXP B.V. 2010. All rights reserved.
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