MC9S08DV32ACLF Freescale Semiconductor, MC9S08DV32ACLF Datasheet - Page 132

• Manufacturer Part Number: MC9S08DV32ACLF
• Description: IC MCU 32K FLASH 2K RAM 48-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of MC9S08DV32ACLF

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 39
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Processor Series: S08DV
• Core: HCS08
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: CAN, I2C, SCI, SPI
• Number Of Programmable I/os: 26
• Operating Supply Voltage: 5.5 V
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWS08
• Development Tools By Supplier: DEMO9S08DZ60
• On-chip Adc: 12 bit, 10 channel
• Controller Family/series: HCS08
• No. Of I/o's: 39
• Ram Memory Size: 2KB
• Cpu Speed: 40MHz
• No. Of Timers: 2
• Digital Ic Case Style: LQFP
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

INH
IMM
DIR
EXT
DD
IX+D
Note: All Sheet 2 Opcodes are Preceded by the Page 2 Prebyte (9E)
Chapter 7 Central Processor Unit (S08CPUV3)
132
Bit-Manipulation
Inherent
Immediate
Direct
Extended
DIR to DIR
IX+ to DIR
Branch
REL
IX
IX1
IX2
IMD
DIX+
Relative
Indexed, No Offset
Indexed, 8-Bit Offset
Indexed, 16-Bit Offset
IMM to DIR
DIR to IX+
Read-Modify-Write
Table 7-3. Opcode Map (Sheet 2 of 2)
SP1
SP2
IX+
IX1+
MC9S08DV60 Series Data Sheet, Rev 3
9E60
3
9E61
4
9E63
3
9E64
3
9E66
3
9E67
3
9E68
3
9E69
3
9E6A
3
9E6B
4
9E6C
3
9E6D
3
9E6F
3
Stack Pointer, 8-Bit Offset
Stack Pointer, 16-Bit Offset
Indexed, No Offset with
Post Increment
Indexed, 1-Byte Offset with
Post Increment
CBEQ
DBNZ
COM
NEG
ROR
DEC
LSR
ASR
ROL
CLR
LSL
TST
INC
SP1
SP1
SP1
SP1
SP1
SP1
SP1
SP1
SP1
SP1
SP1
SP1
SP1
6
6
6
6
6
6
6
6
6
8
6
5
6
Control
Prebyte (9E) and Opcode in
9EAE
2
LDHX
Number of Bytes
IX
5
Hexadecimal
9EBE
4
LDHX
IX2
6
9ECE
3
9E60
3
LDHX
Register/Memory
NEG
SP1
IX1
Freescale Semiconductor
5
6
9ED0
4
9ED1
4
9ED2
4
9ED3
4
9ED4
4
9ED5
4
9ED6
4
9ED7
4
9ED8
4
9ED9
4
9EDA
4
9EDB
4
9EDE
4
9EDF
4
HCS08 Cycles
Instruction Mnemonic
Addressing Mode
CMP
SUB
SBC
CPX
AND
EOR
ADC
ORA
ADD
LDA
LDX
STX
STA
BIT
SP2
SP2
SP2
SP2
SP2
SP2
SP2
SP2
SP2
SP2
SP2
SP2
SP2
SP2
5
5
5
5
5
5
5
5
5
5
5
5
5
5
9EE0
3
9EE1
3
9EE2
3
9EE3
3
9EE4
3
9EE5
3
9EE6
3
9EE7
3
9EE8
3
9EE9
3
9EEA
3
9EEB
3
9EEE
3
9EEF
3
CMP
EOR
ORA
SUB
SBC
CPX
AND
ADC
ADD
LDA
STA
LDX
STX
BIT
SP1
SP1
SP1
SP1
SP1
SP1
SP1
SP1
SP1
SP1
SP1
SP1
SP1
SP1
4
4
4
4
4
4
4
4
4
4
4
4
4
4
9EF3
3
9EFE
3
9EFF
3
CPHX
LDHX
STHX
SP1
SP1
SP1
6
5
5