MC9S08DV32ACLF Freescale Semiconductor, MC9S08DV32ACLF Datasheet - Page 15

• Manufacturer Part Number: MC9S08DV32ACLF
• Description: IC MCU 32K FLASH 2K RAM 48-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of MC9S08DV32ACLF

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 39
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Processor Series: S08DV
• Core: HCS08
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: CAN, I2C, SCI, SPI
• Number Of Programmable I/os: 26
• Operating Supply Voltage: 5.5 V
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWS08
• Development Tools By Supplier: DEMO9S08DZ60
• On-chip Adc: 12 bit, 10 channel
• Controller Family/series: HCS08
• No. Of I/o's: 39
• Ram Memory Size: 2KB
• Cpu Speed: 40MHz
• No. Of Timers: 2
• Digital Ic Case Style: LQFP
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Section Number
12.4 Programmer’s Model of Message Storage .....................................................................................239
12.5 Functional Description ...................................................................................................................248
12.6 Initialization/Application Information ...........................................................................................268
13.1 Introduction ....................................................................................................................................271
13.2 External Signal Description ...........................................................................................................276
13.3 Modes of Operation........................................................................................................................277
13.4 Register Definition .........................................................................................................................277
13.5 Functional Description ...................................................................................................................282
Freescale Semiconductor
12.3.15MSCAN Identifier Acceptance Registers (CANIDAR0-7) ............................................237
12.3.16MSCAN Identifier Mask Registers (CANIDMR0–CANIDMR7) .................................238
12.4.1 Identifier Registers (IDR0–IDR3) ...................................................................................242
12.4.2 IDR0–IDR3 for Standard Identifier Mapping .................................................................244
12.4.3 Data Segment Registers (DSR0-7) .................................................................................245
12.4.4 Data Length Register (DLR) ...........................................................................................246
12.4.5 Transmit Buffer Priority Register (TBPR) ......................................................................247
12.4.6 Time Stamp Register (TSRH–TSRL) .............................................................................247
12.5.1 General ............................................................................................................................248
12.5.2 Message Storage .............................................................................................................249
12.5.3 Identifier Acceptance Filter .............................................................................................252
12.5.4 Modes of Operation ........................................................................................................259
12.5.5 Low-Power Options ........................................................................................................260
12.5.6 Reset Initialization ..........................................................................................................266
12.5.7 Interrupts .........................................................................................................................266
12.6.1 MSCAN initialization .....................................................................................................268
12.6.2 Bus-Off Recovery ...........................................................................................................269
13.1.1 Features ...........................................................................................................................273
13.1.2 Block Diagrams ..............................................................................................................273
13.1.3 SPI Baud Rate Generation ..............................................................................................275
13.2.1 SPSCK — SPI Serial Clock ............................................................................................276
13.2.2 MOSI — Master Data Out, Slave Data In ......................................................................276
13.2.3 MISO — Master Data In, Slave Data Out ......................................................................276
13.2.4 SS — Slave Select ...........................................................................................................276
13.3.1 SPI in Stop Modes ..........................................................................................................277
13.4.1 SPI Control Register 1 (SPIC1) ......................................................................................277
13.4.2 SPI Control Register 2 (SPIC2) ......................................................................................278
13.4.3 SPI Baud Rate Register (SPIBR) ....................................................................................279
13.4.4 SPI Status Register (SPIS) ..............................................................................................280
13.4.5 SPI Data Register (SPID) ................................................................................................281
13.5.1 SPI Clock Formats ..........................................................................................................282
Serial Peripheral Interface (S08SPIV3)
MC9S08DV60 Series Data Sheet, Rev 3
Chapter 13
Subject to Change
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