MC9S08DV32ACLF Freescale Semiconductor, MC9S08DV32ACLF Datasheet - Page 53

• Manufacturer Part Number: MC9S08DV32ACLF
• Description: IC MCU 32K FLASH 2K RAM 48-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of MC9S08DV32ACLF

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 39
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Processor Series: S08DV
• Core: HCS08
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: CAN, I2C, SCI, SPI
• Number Of Programmable I/os: 26
• Operating Supply Voltage: 5.5 V
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWS08
• Development Tools By Supplier: DEMO9S08DZ60
• On-chip Adc: 12 bit, 10 channel
• Controller Family/series: HCS08
• No. Of I/o's: 39
• Ram Memory Size: 2KB
• Cpu Speed: 40MHz
• No. Of Timers: 2
• Digital Ic Case Style: LQFP
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

4.5.2
Before any program or erase command can be accepted, the Flash clock divider register (FCDIV) must be
written to set the internal clock for the Flash module to a frequency (f
(see
so normally this write is performed during reset initialization. The user must ensure that FACCERR is not
set before writing to the FCDIV register. One period of the resulting clock (1/f
command processor to time program and erase pulses. An integer number of these timing pulses is used
by the command processor to complete a program or erase command.
Table 4-6
of FCLK (f
of cycles of FCLK and as an absolute time for the case where t
shown include overhead for the command state machine and enabling and disabling of program and erase
voltages.
4.5.3
The FCDIV register must be initialized after any reset and any error flag is cleared before beginning
command execution. The command execution steps are:
1. A mass erase is possible only when the Flash block is fully unprotected.
Freescale Semiconductor
1. Write a data value to an address in the Flash array. The address and data information from this write
2. Write the command code for the desired command to FCMD. The six valid commands are blank
Section 4.5.10.1, “Flash Clock Divider Register
is latched into the Flash interface. This write is a required first step in any command sequence. For
erase and blank check commands, the value of the data is not important. For sector erase
commands, the address can be any address in the sector of Flash to be erased. For mass erase and
blank check commands, the address can be any address in the Flash .
check (0x05), byte program (0x20), burst program (0x25), sector erase (0x40), mass erase
and sector erase abort (0x47). The command code is latched into the command buffer.
shows program and erase times. The bus clock frequency and FCDIV determine the frequency
FCLK
Program and Erase Times
Program and Erase Command Execution
1
Before programming a particular byte in the Flash , the sector in which that
particular byte resides must be erased by a mass or sector erase operation.
Reprogramming bits in an already programmed byte without first
performing an erase operation may disturb data stored in the Flash memory.
Excluding start/end overhead
). The time for one cycle of FCLK is t
Sector erase abort
Burst program
Byte program
Sector erase
Mass erase
Parameter
Table 4-6. Program and Erase Times
MC9S08DV60 Series Data Sheet, Rev 3
Cycles of FCLK
NOTE
20,000
4000
9
4
4
(FCDIV)”). This register can be written only once,
FCLK
= 1/f
FCLK
FCLK
FCLK
Time if FCLK = 200 kHz
= 5 μs. Program and erase times
. The times are shown as a number
) between 150 kHz and 200 kHz
100 ms
20 μs
20 μs
20 ms
45 μs
FCLK
1
1
) is used by the
Chapter 4 Memory
1
(0x41),
53