MC9S08DV32ACLF Freescale Semiconductor, MC9S08DV32ACLF Datasheet - Page 58

• Manufacturer Part Number: MC9S08DV32ACLF
• Description: IC MCU 32K FLASH 2K RAM 48-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of MC9S08DV32ACLF

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 39
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Processor Series: S08DV
• Core: HCS08
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: CAN, I2C, SCI, SPI
• Number Of Programmable I/os: 26
• Operating Supply Voltage: 5.5 V
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWS08
• Development Tools By Supplier: DEMO9S08DZ60
• On-chip Adc: 12 bit, 10 channel
• Controller Family/series: HCS08
• No. Of I/o's: 39
• Ram Memory Size: 2KB
• Cpu Speed: 40MHz
• No. Of Timers: 2
• Digital Ic Case Style: LQFP
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Chapter 4 Memory
4.5.6
An access error occurs whenever the command execution protocol is violated.
Any of the following specific actions will cause the access error flag (FACCERR) in FSTAT to be set.
FACCERR must be cleared by writing a 1 to FACCERR in FSTAT before any command can be processed.
58
•
•
•
•
•
•
•
•
•
•
Writing to a Flash address before the internal Flash clock frequency has been set by writing to the
FCDIV register.
Writing to a Flash address while FCBEF is not set. (A new command cannot be started until the
command buffer is empty.)
Writing a second time to a Flash address before launching the previous command. (There is only
one write to Flash for every command.)
Writing a second time to FCMD before launching the previous command. (There is only one write
to FCMD for every command.)
Writing to any Flash control register other than FCMD after writing to a Flash address.
Writing any command code other than the six allowed codes (0x05, 0x20, 0x25, 0x40, 0x41, or
0x47) to FCMD.
Writing any Flash control register other than to write to FSTAT (to clear FCBEF and launch the
command) after writing the command to FCMD.
The MCU enters stop mode while a program or erase command is in progress. (The command is
aborted.)
Writing the byte program, burst program, sector erase or sector erase abort command code (0x20,
0x25, 0x40, or 0x47) with a background debug command while the MCU is secured. (The
background debug controller can do blank check and mass erase commands only when the MCU
is secure.)
Writing 0 to FCBEF to cancel a partial command.
Access Errors
The FCBEF flag will not set after launching the sector erase abort command.
If an attempt is made to start a new command write sequence with a sector
erase abort operation active, the FACCERR flag in the FSTAT register will
be set. A new command write sequence may be started after clearing the
ACCERR flag, if set.
The sector erase abort command should be used sparingly since a sector
erase operation that is aborted counts as a complete program/erase cycle.
MC9S08DV60 Series Data Sheet, Rev 3
NOTE
NOTE
Freescale Semiconductor