MC9S08DV32ACLF Freescale Semiconductor, MC9S08DV32ACLF Datasheet - Page 258

• Manufacturer Part Number: MC9S08DV32ACLF
• Description: IC MCU 32K FLASH 2K RAM 48-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of MC9S08DV32ACLF

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 39
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Processor Series: S08DV
• Core: HCS08
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: CAN, I2C, SCI, SPI
• Number Of Programmable I/os: 26
• Operating Supply Voltage: 5.5 V
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWS08
• Development Tools By Supplier: DEMO9S08DZ60
• On-chip Adc: 12 bit, 10 channel
• Controller Family/series: HCS08
• No. Of I/o's: 39
• Ram Memory Size: 2KB
• Cpu Speed: 40MHz
• No. Of Timers: 2
• Digital Ic Case Style: LQFP
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Chapter 12 Freescale’s Controller Area Network (S08MSCANV1)
If the bus clock is generated from a PLL, it is recommended to select the oscillator clock rather than the
bus clock due to jitter considerations, especially at the faster CAN bus rates. PLL lock may also be too
wide to ensure adequate clock tolerance.
For microcontrollers without a clock and reset generator (CRG), CANCLK is driven from the crystal
oscillator (oscillator clock).
A programmable prescaler generates the time quanta (Tq) clock from CANCLK. A time quantum is the
atomic unit of time handled by the MSCAN.
A bit time is subdivided into three segments as described in the Bosch CAN specification. (see
Figure
258
•
•
•
12-43):
SYNC_SEG: This segment has a fixed length of one time quantum. Signal edges are expected to
happen within this section.
Time Segment 1: This segment includes the PROP_SEG and the PHASE_SEG1 of the CAN
standard. It can be programmed by setting the parameter TSEG1 to consist of 4 to 16 time quanta.
Time Segment 2: This segment represents the PHASE_SEG2 of the CAN standard. It can be
programmed by setting the TSEG2 parameter to be 2 to 8 time quanta long.
Transmit Point
SYNC_SEG
1
Bit Rate
NRZ Signal
Figure 12-43. Segments within the Bit Time
MC9S08DV60 Series Data Sheet, Rev 3
(PROP_SEG + PHASE_SEG1)
Tq
=
=
8 ... 25 Time Quanta
-------------------------------------------------------------------------------- -
(
Time Segment 1
number of Time Quanta
----------------------------------------------------- -
(
= 1 Bit Time
4 ... 16
Prescaler value
f
CANCLK
f
Tq
Sample Point
(single or triple sampling)
)
Time Segment 2
(PHASE_SEG2)
2 ... 8
)
Freescale Semiconductor
Eqn. 12-2
Eqn. 12-3