MC9S08DV32ACLF Freescale Semiconductor, MC9S08DV32ACLF Datasheet - Page 338

• Manufacturer Part Number: MC9S08DV32ACLF
• Description: IC MCU 32K FLASH 2K RAM 48-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of MC9S08DV32ACLF

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 39
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Processor Series: S08DV
• Core: HCS08
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: CAN, I2C, SCI, SPI
• Number Of Programmable I/os: 26
• Operating Supply Voltage: 5.5 V
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWS08
• Development Tools By Supplier: DEMO9S08DZ60
• On-chip Adc: 12 bit, 10 channel
• Controller Family/series: HCS08
• No. Of I/o's: 39
• Ram Memory Size: 2KB
• Cpu Speed: 40MHz
• No. Of Timers: 2
• Digital Ic Case Style: LQFP
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Chapter 16 Timer/PWM Module (S08TPMV3)
All TPM interrupts are listed in
that can block the interrupt request from leaving the TPM and getting recognized by the separate interrupt
processing logic.
The TPM module will provide a high-true interrupt signal. Vectors and priorities are determined at chip
integration time in the interrupt module so refer to the user’s guide for the interrupt module or to the chip’s
complete documentation for details.
16.6.2
For each interrupt source in the TPM, a flag bit is set upon recognition of the interrupt condition such as
timer overflow, channel-input capture, or output-compare events. This flag may be read (polled) by
software to determine that the action has occurred, or an associated enable bit (TOIE or CHnIE) can be set
to enable hardware interrupt generation. While the interrupt enable bit is set, a static interrupt will generate
whenever the associated interrupt flag equals one. The user’s software must perform a sequence of steps
to clear the interrupt flag before returning from the interrupt-service routine.
TPM interrupt flags are cleared by a two-step process including a read of the flag bit while it is set (1)
followed by a write of zero (0) to the bit. If a new event is detected between these two steps, the sequence
is reset and the interrupt flag remains set after the second step to avoid the possibility of missing the new
event.
16.6.2.1
The meaning and details of operation for TOF interrupts varies slightly depending upon the mode of
operation of the TPM system (general purpose timing functions versus center-aligned PWM operation).
The flag is cleared by the two step sequence described above.
16.6.2.1.1
Normally TOF is set when the timer counter changes from 0xFFFF to 0x0000. When the TPM is not
configured for center-aligned PWM (CPWMS=0), TOF gets set when the timer counter changes from the
terminal count (the value in the modulo register) to 0x0000. This case corresponds to the normal meaning
of counter overflow.
338
Description of Interrupt Operation
Interrupt
Timer Overflow Interrupt (TOF) Description
CHnF
TOF
Normal Case
Enable
CHnIE
Local
TOIE
Table 16-8
Counter overflow
MC9S08DV60 Series Data Sheet, Rev 3
Channel event
Table 16-8. Interrupt Summary
Source
which shows the interrupt name, the name of any local enable
Set each time the timer counter reaches its terminal
count (at transition to next count value which is
usually 0x0000)
An input capture or output compare event took
place on channel n
Description
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