D6417709SHF200BV Renesas Electronics America, D6417709SHF200BV Datasheet - Page 127
![IC SUPER H MPU ROMLESS 208LQFP](/photos/12/31/123130/d6417709shf200bv_sml.jpg)
D6417709SHF200BV
Manufacturer Part Number
D6417709SHF200BV
Description
IC SUPER H MPU ROMLESS 208LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.D6417709SBP167BV.pdf
(809 pages)
Specifications of D6417709SHF200BV
Core Processor
SH-3
Core Size
32-Bit
Speed
200MHz
Connectivity
EBI/EMI, FIFO, IrDA, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
96
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.85 V ~ 2.15 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
208-QFP Exposed Pad, 208-eQFP, 208-HQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
D6417709SHF200BV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 127 of 809
- Download datasheet (5Mb)
In the address field, specify VPN in bits 16-12 as the index address that selects the entry, W in bits
9-8 to select the way, and H'F2 in bits 31-24 to indicate access to the address array. Selection of
the index address depends on the MMUCR.IX setting.
The following 2 types of operations on the address array are possible.
(1) Address Array Read
(2) Address Array Write
3.6.2
The data array is assigned to H'F3000000 to H'F3FFFFFF. To access a data array, the 32-bit
address field (for read/write operations), and 32-bit data field (for write operations) must be
specified. These are specified in the general register. The address section specifies information for
selecting the entry to be accessed; the data section specifies the longword data to be written to the
data array (figure 3.14 (2)).
In the address section, specify the entry address for selecting the entry (bits 16–12), W for
selecting the way (bits 9–8: 00 is way 0, 01 is way 1, 10 is way 2, 11 is way 3), and H'F3 to
indicate data array access (bits 31–24). The IX bit in MMUCR indicates whether an EX-OR is
taken of the entry address and ASID.
Both reading and writing use the longword of the data array specified by the index address and
way number. The access size of the data array is fixed at longword.
Reads VPN, V bit, and ASID from the entry that corresponds to the entry address and way that
were specified in the address field.
Writes the data set in the data field to the entry that corresponds to the entry address and way
that were specified in the address field.
Data Array
Rev. 5.00, 09/03, page 81 of 760
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