D6417709SHF200BV Renesas Electronics America, D6417709SHF200BV Datasheet - Page 234
D6417709SHF200BV
Manufacturer Part Number
D6417709SHF200BV
Description
IC SUPER H MPU ROMLESS 208LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.D6417709SBP167BV.pdf
(809 pages)
Specifications of D6417709SHF200BV
Core Processor
SH-3
Core Size
32-Bit
Speed
200MHz
Connectivity
EBI/EMI, FIFO, IrDA, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
96
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.85 V ~ 2.15 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
208-QFP Exposed Pad, 208-eQFP, 208-HQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
D6417709SHF200BV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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8.4
8.4.1
To enter standby mode, set the STBY bit to 1 in STBCR, then execute the SLEEP instruction. The
chip switches from the program execution state to standby mode. In standby mode, power
consumption is greatly reduced by halting not only the CPU, but the clock and on-chip peripheral
modules as well. The clock output from the CKIO and CKIO2 pins also halts. CPU and cache
register contents are held, but some on-chip peripheral modules are initialized. Table 8.4 lists the
states of registers in standby mode.
Table 8.4
Module
Interrupt controller (INTC)
On-chip clock pulse generator
(OSC)
User break controller (UBC)
Bus state controller (BSC)
Timer unit (TMU)
Realtime clock (RTC)
A/D converter (ADC)
D/A converter (DAC)
The procedure for moving to standby mode is as follows:
1. Clear the TME bit in the WDT’s timer control register (WTCSR) to 0 to stop the WDT. Clear
2. After the STBY bit in the STBCR register is set to 1, a SLEEP instruction is executed.
3. Standby mode is entered and the clocks within the chip are halted. The STATUS1 pin output
Rev. 5.00, 09/03, page 188 of 760
the WDT’s timer counter (WTCNT) to 0 and the CKS2–CKS0 bits in the WTCSR register to
appropriate values to secure the specified oscillation settling time.
goes low and the STATUS0 pin output goes high.
Standby Mode
Transition to Standby Mode
Register States in Standby Mode
Registers Initialized
—
—
—
—
TSTR register
—
All registers
—
Registers Retaining Data
All registers
All registers
All registers
All registers
Registers other than TSTR
All registers
—
All registers
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