D6417709SHF200BV Renesas Electronics America, D6417709SHF200BV Datasheet - Page 387
![IC SUPER H MPU ROMLESS 208LQFP](/photos/12/31/123130/d6417709shf200bv_sml.jpg)
D6417709SHF200BV
Manufacturer Part Number
D6417709SHF200BV
Description
IC SUPER H MPU ROMLESS 208LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.D6417709SBP167BV.pdf
(809 pages)
Specifications of D6417709SHF200BV
Core Processor
SH-3
Core Size
32-Bit
Speed
200MHz
Connectivity
EBI/EMI, FIFO, IrDA, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
96
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.85 V ~ 2.15 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
208-QFP Exposed Pad, 208-eQFP, 208-HQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
D6417709SHF200BV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Bit 6—D D D D R R R R E E E E Q Q Q Q Select Bit (DS): Selects low-level or falling-edge detection as the sampling method
for the DREQ pin used in external request mode.
This bit is only valid in CHCR0 and CHCR1. Writing to this bit is invalid in CHCR2 and
CHCR3; 0 is read if this bit is read. The write value should always be 0.
In channels 0 and 1, if an on-chip peripheral module is specified as a transfer request source or an
auto-request is specified, the specification of this bit is ignored and falling-edge detection is fixed
except in an auto-request.
Bit 5—Transmit Mode (TM): Specifies the bus mode when transferring data.
Bits 4 and 3—Transmit Size Bits 1 and 0 (TS1, TS0): Specify the size of data to be transferred.
Bit 2—Interrupt Enable Bit (IE): If this bit is set to 1, an interrupt is requested on completion of
the number of data transfers specified in DMATCR (i.e. when TE = 1).
Bit 6: DS
0
1
Bit 5: TM
0
1
Bit 4: TS1
0
0
1
1
Bit 2: IE
0
1
Bit 3: TS0
0
1
0
1
Description
DREQ detected by low level
DREQ detected at falling edge
Description
Cycle-steal mode
Burst mode
Description
Interrupt request is not generated on completion of data transfers
specified in DMATCR
Interrupt request is generated on completion of data transfers specified
in DMATCR
Description
Byte size (8 bits)
Word size (16 bits)
Longword size (32 bits)
16-byte unit (4 longword transfers)
Rev. 5.00, 09/03, page 341 of 760
(Initial value)
(Initial value)
(Initial value)
(Initial value)
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