D6417709SHF200BV Renesas Electronics America, D6417709SHF200BV Datasheet - Page 555
D6417709SHF200BV
Manufacturer Part Number
D6417709SHF200BV
Description
IC SUPER H MPU ROMLESS 208LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.D6417709SBP167BV.pdf
(809 pages)
Specifications of D6417709SHF200BV
Core Processor
SH-3
Core Size
32-Bit
Speed
200MHz
Connectivity
EBI/EMI, FIFO, IrDA, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
96
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.85 V ~ 2.15 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
208-QFP Exposed Pad, 208-eQFP, 208-HQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
D6417709SHF200BV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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15.4.2
Retransmission when SCI is in Receive Mode: Figure 15.9 shows the retransmission operation
in the SCI receive mode.
1. When the received parity bit is checked and an error is found, the PER bit in SCSSR is
2. The RDRF bit in SCSSR is not set in the frame that caused the error.
3. When the received parity bit is checked and no error is found, the PER bit in SCSSR is not set.
4. When the received parity bit is checked and no error is found, reception is considered to have
5. When a normal frame is received, the pin maintains a three-state state when it transmits the
automatically set to 1. If the RIE bit in SCSCR is enabled at this time, an ERI interrupt is
requested. Be sure to clear the PER bit before the next parity bit is sampled.
been completed normally and the RDRF bit in SCSSR is automatically set to 1. If the RIE bit
in SCSCR is enabled at this time, an RXI interrupt is requested.
error signal.
RDRF
PER
Ds
D0
D1
Retransmission (Receive and Transmit Modes)
nth transfer frame
D2
D3
D4
D5
Figure 15.9 Retransmission in SCI Receive Mode
D6
D7
Dp DE
2
1
Ds
D0
D1
Retransmitted frame
D2
D3
D4
D5
D6
D7
Dp
Rev. 5.00, 09/03, page 509 of 760
(DE)
5
4
3
Ds
Transfer frame n + 1
D0
D1
D2
D3
D4
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