D6417709SHF200BV Renesas Electronics America, D6417709SHF200BV Datasheet - Page 140
D6417709SHF200BV
Manufacturer Part Number
D6417709SHF200BV
Description
IC SUPER H MPU ROMLESS 208LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.D6417709SBP167BV.pdf
(809 pages)
Specifications of D6417709SHF200BV
Core Processor
SH-3
Core Size
32-Bit
Speed
200MHz
Connectivity
EBI/EMI, FIFO, IrDA, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
96
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.85 V ~ 2.15 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
208-QFP Exposed Pad, 208-eQFP, 208-HQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
D6417709SHF200BV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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4.4.3
When the SH7709S encounters any exception condition other than a reset or interrupt request, it
executes the following operations:
1. The contents of PC and SR are saved to SPC and SSR, respectively.
2. The BL bit in SR is set to 1, masking any subsequent exceptions (except the NMI interrupt
3. The MD bit in SR is set to 1 to place the SH7709S in privileged mode.
4. The RB bit in SR is set to 1.
5. Instruction execution jumps to the vector location designated by either the sum of the vector
4.5
This section describes the conditions for specific exception handling, and this LSI operations.
4.5.1
Rev. 5.00, 09/03, page 94 of 760
when the BLMSK bit is 1).
base address and offset H'00000400 in the vector table in a TLB miss trap, or by the sum of the
vector base address and offset H'00000100 for exceptions other than TLB miss traps, to invoke
the exception handler.
Power-On Reset
Manual Reset
Conditions: RESETP low
Operations: EXPEVT set to H'000, VBR and SR initialized, branch to PC
Initialization sets the VBR register to H'0000000. In SR, the MD, RB and BL bits are set to
1 and the interrupt mask bits (I3 to I0) are set to B'1111. The CPU and on-chip peripheral
modules are initialized. See the register descriptions in the relevant sections for details. A
power-on reset must always be performed when powering on. A low level is output from
the RESETOUT pin, and a high level is output from the STATUS0 and STATUS1 pins.
Conditions: RESETM low
Operations: EXPEVT set to H'020, VBR and SR initialized, branch to PC
Initialization sets the VBR register to H'0000000. In SR, the MD, RB, and BL bits are set
to 1 and the interrupt mask bits (I3 to I0) are set to B'1111. The CPU and on-chip
peripheral modules are initialized. See the register descriptions in the relevant sections for
details. A low level is output from the RESETOUT pin, and a high level is output from the
STATUS0 and STATUS1 pins.
General Exceptions
Individual Exception Operations
Resets
H'A0000000.
H'A0000000.
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