D6417709SHF200BV Renesas Electronics America, D6417709SHF200BV Datasheet - Page 489
![IC SUPER H MPU ROMLESS 208LQFP](/photos/12/31/123130/d6417709shf200bv_sml.jpg)
D6417709SHF200BV
Manufacturer Part Number
D6417709SHF200BV
Description
IC SUPER H MPU ROMLESS 208LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.D6417709SBP167BV.pdf
(809 pages)
Specifications of D6417709SHF200BV
Core Processor
SH-3
Core Size
32-Bit
Speed
200MHz
Connectivity
EBI/EMI, FIFO, IrDA, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
96
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.85 V ~ 2.15 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
208-QFP Exposed Pad, 208-eQFP, 208-HQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
D6417709SHF200BV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Bit 2—Transmit End (TEND): Indicates that when the last bit of a serial character was
transmitted, SCTDR did not contain valid data, so transmission has ended. TEND is a read-only
bit and cannot be written to.
Bit 1—Multiprocessor Bit (MPB): Stores the value of the multiprocessor bit in receive data
when a multiprocessor format is selected for receiving in asynchronous mode. MPB is a read-only
bit and cannot be written to.
Note: * If RE is cleared to 0 when a multiprocessor format is selected, MPB retains its
Bit 0—Multiprocessor Bit Transfer (MPBT): Stores the value of the multiprocessor bit added to
transmit data when a multiprocessor format is selected for transmitting in asynchronous mode.
The MPBT setting is ignored in synchronous mode, when a multiprocessor format is not selected,
or when the SCI is not transmitting.
Bit 2: TEND
0
1
Bit 1: MPB
0
1
Bit 0: MPBT
0
1
previous value.
Description
Transmission is in progress
[Clearing condition]
TEND is cleared to 0 when software reads TDRE after it has been set to 1, then
writes 0 to TDRE.
End of transmission
[Setting conditions]
(1) TEND is set to 1 when the chip is reset or enters standby mode.
(2) When TE is cleared to 0 in the serial control register (SCSCR).
(3) If TDRE is 1 when the last bit of a one-byte serial character is transmitted.
Description
Multiprocessor bit value in receive data is 0 *
Multiprocessor bit value in receive data is 1
Description
Multiprocessor bit value in transmit data is 0
Multiprocessor bit value in transmit data is 1
Rev. 5.00, 09/03, page 443 of 760
(Initial value)
(Initial value)
(Initial value)
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