D6417709SHF200BV Renesas Electronics America, D6417709SHF200BV Datasheet - Page 153
![IC SUPER H MPU ROMLESS 208LQFP](/photos/12/31/123130/d6417709shf200bv_sml.jpg)
D6417709SHF200BV
Manufacturer Part Number
D6417709SHF200BV
Description
IC SUPER H MPU ROMLESS 208LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.D6417709SBP167BV.pdf
(809 pages)
Specifications of D6417709SHF200BV
Core Processor
SH-3
Core Size
32-Bit
Speed
200MHz
Connectivity
EBI/EMI, FIFO, IrDA, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
96
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.85 V ~ 2.15 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
208-QFP Exposed Pad, 208-eQFP, 208-HQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
D6417709SHF200BV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Whenever CCR2 bit 8 (W3LOCK) or bit 0 (W2LOCK) is high the cache is locked. The locked
data will not be overwritten unless W3LOCK bit and W2LOCK bit are reset or the PREF
condition during DSP mode matched. During cache locking mode, the LRU in table 5.2 will be
replaced by tables 5.4 to 5.8.
Table 5.4
DSP bit
0
1
1
1
1
1
1
*: Don't care
Do not set as W3LOAD=1 and also W2LOAD=1
W2LOCK: Way 2 lock bit. W2LOAD: Way 2 load bit.
When W2LOCK = 1 & W2LOAD = 1 & SR, CL = 1, the prefetched data will always be
loaded into Way2. In all other conditions the prefetched data will be loaded into the way
pointed by LRU.
W3LOCK: Way 3 lock bit. W3LOAD: Way 3 load bit.
When W3LOCK = 1 & W3LOAD = 1 & SR, CL = 1, the prefetched data will always be
loaded into Way3. In all other conditions the prefetched data will be loaded into the way
pointed by LRU.
Note: W2LOAD and W3LOAD should not be set to high at the same time.
—: Reserved bits.
31
*
*
*
0
0
0
1
W3LOAD
Way Replacement when PREF Instruction Ended Up in a Cache Miss
W3LOCK
*
0
0
1
1
*
1
Figure 5.3 CCR2 Register Configuration
W2LOAD
*
*
0
*
0
1
0
W2LOCK
*
0
1
0
1
1
*
LOAD
W3
9
LOCK
W3
8
Way to be replaced
Depends on LRU (table 5.2)
Depends on LRU (table 5.2)
Depends on LRU (table 5.6)
Depends on LRU (table 5.7)
Depends on LRU (table 5.8)
Way 2
Way 3
7
Rev. 5.00, 09/03, page 107 of 760
2
LOAD
W2
1
LOCK
W2
0
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