D6417709SHF200BV Renesas Electronics America, D6417709SHF200BV Datasheet - Page 225
![IC SUPER H MPU ROMLESS 208LQFP](/photos/12/31/123130/d6417709shf200bv_sml.jpg)
D6417709SHF200BV
Manufacturer Part Number
D6417709SHF200BV
Description
IC SUPER H MPU ROMLESS 208LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.D6417709SBP167BV.pdf
(809 pages)
Specifications of D6417709SHF200BV
Core Processor
SH-3
Core Size
32-Bit
Speed
200MHz
Connectivity
EBI/EMI, FIFO, IrDA, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
96
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.85 V ~ 2.15 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
208-QFP Exposed Pad, 208-eQFP, 208-HQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
D6417709SHF200BV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 225 of 809
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7.3.8
1. Only CPU can read/write UBC registers.
2. UBC cannot monitor CPU and DMAC access in the same channel.
3. Notes in specification of sequential break are described below:
4. The change of a UBC register value is executed in MA (memory access) stage. Therefore,
5. The branch instruction should not be executed as soon as PC trace register BRSR and BRDR
6. When PC breaks and TLB exceptions or errors occur in the same instruction. The priority is as
a. A condition match occurs when B-channel match occurs in a bus cycle after an A-channel
b. Since the CPU has a pipeline configuration, the pipeline determines the order of an
c. When the bus cycle condition for channel A is specified as a break before execution
even if the break condition matches in the instruction fetch address following the instruction in
which the pre-execution break is specified as the break condition, no break occurs. In order to
know the timing UBC register is changed, read the last written register. Instructions after then
are valid for the newly written register value.
are read.
follows:
a. Break and instruction fetch exceptions: Instruction fetch exception occurs first.
b. Break before execution and operand exception: Break before execution occurs first.
c. Break after execution and operand exception: Operand exception occurs first.
match occurs in another bus cycle in sequential break setting. Therefore, no condition
match occurs even if a bus cycle, in which an A-channel match and a channel B match
occur simultaneously, is set.
instruction fetch cycle and a memory cycle. Therefore, when a channel condition matches
in the order of bus cycles, a sequential condition is satisfied.
(PCBA = 0 in BRCR) and an instruction fetch cycle (in BBRA), the attention is as follows.
A break is issued and condition match flags in BRCR are set to 1, when the bus cycle
conditions both for channels A and B match simultaneously.
Notes
Rev. 5.00, 09/03, page 179 of 760
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