D6417709SHF200BV Renesas Electronics America, D6417709SHF200BV Datasheet - Page 179
D6417709SHF200BV
Manufacturer Part Number
D6417709SHF200BV
Description
IC SUPER H MPU ROMLESS 208LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.D6417709SBP167BV.pdf
(809 pages)
Specifications of D6417709SHF200BV
Core Processor
SH-3
Core Size
32-Bit
Speed
200MHz
Connectivity
EBI/EMI, FIFO, IrDA, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
96
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.85 V ~ 2.15 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
208-QFP Exposed Pad, 208-eQFP, 208-HQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
D6417709SHF200BV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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6.3.3
ICR1 is a 16-bit register that specifies the detection mode for external interrupt input pins IRQ0 to
IRQ5 individually: rising edge, falling edge, or low level. This register is initialized to H'4000 by a
power-on reset or manual reset, but is not initialized in standby mode.
Bit 15—Mask All Interrupts (MAI): When set to 1, all interrupt requests are masked while a
low level is being input to the NMI pin. Masks NMI interrupts in standby mode.
Bit 14—Interrupt Request Level Detect (IRQLVL): Selects whether the IRQ3–IRQ0 pins are
used as four independent interrupt pins or as 15-level interrupt pins encoded as IRL3–IRL0.
Bit 13—BL Bit Mask (BLMSK): Specifies whether NMI interrupts are masked when the BL bit
in the SR register is 1.
Bit 15: MAI
0
1
Bit 14: IRQLVL Description
0
1
Bit 13: BLMSK Description
0
1
Initial value:
Initial value:
Interrupt Control Register 1 (ICR1)
R/W:
R/W:
Bit:
Bit:
Description
All interrupt requests are not masked when NMI pin is low level
All interrupt requests are masked when NMI pin is low level
Used as four independent interrupt request pins IRQ3–IRQ0
Used as 15-level interrupt pins encoded as IRL3–IRL0
NMI interrupts are masked when BL bit is 1
NMI interrupts are accepted regardless of BL bit setting
IRQ31S IRQ30S IRQ21S IRQ20S IRQ11S IRQ10S IRQ01S IRQ00S
R/W
R/W
MAI
15
0
7
0
IRQLVL BLMSK IRLSEN IRQ51S IRQ50S IRQ41S IRQ40S
R/W
R/W
14
1
6
0
R/W
R/W
13
0
5
0
R/W
RW
12
0
4
0
R/W
R/W
11
0
3
0
Rev. 5.00, 09/03, page 133 of 760
R/W
R/W
10
0
2
0
R/W
R/W
9
0
1
0
(Initial value)
(Initial value)
(Initial value)
R/W
R/W
8
0
0
0
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