D6417709SHF200BV Renesas Electronics America, D6417709SHF200BV Datasheet - Page 133

• Manufacturer Part Number: D6417709SHF200BV
• Description: IC SUPER H MPU ROMLESS 208LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of D6417709SHF200BV

• Core Processor: SH-3
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 96
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.85 V ~ 2.15 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 208-QFP Exposed Pad, 208-eQFP, 208-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Table 4.2
Notes: 1. Priorities are indicated from high to low, 1 being the highest and 4 the lowest.
Exception
Type
Reset
General
exception
events
General
interrupt
requests
2. The user defines the break point traps. 1 is a break point before instruction execution
3. Use software to specify relative priorities of external hardware interrupts and peripheral
and 11 is a break point after instruction execution. For an operand break point, use 11.
module interrupts (see section 6, Interrupt Controller (INTC)).
Current
Instruction Exception Event
Aborted
Aborted
and retried
Completed Unconditional trap
Completed Nonmaskable interrupt 3
Exception Event Vectors
Power-on reset
Manual reset
UDI reset
CPU address error
(instruction access)
TLB miss
TLB invalid
(instruction access)
TLB protection
violation (instruction
access)
General illegal
instruction exception
Illegal slot instruction
exception
CPU address error
(data access)
TLB miss (data access
not in repeat loop)
TLB invalid (data
access)
TLB protection
violation (data access)
Initial page write
(TRAPA instruction)
User breakpoint trap
DMA address error
External hardware
interrupt
UDI interrupt
Priority *
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
4 *
4 *
3
3
1
Exception
Order
—
—
1
2
3
4
5
5
6
7
8
9
5
n *
—
—
—
—
10
—
2
Rev. 5.00, 09/03, page 87 of 760
Vector
Address
H'A00000000 —
H'A00000000 —
H'A00000000 —
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Vector
Offset
H'00000100
H'00000400
H'00000100
H'00000100
H'00000100
H'00000100
H'00000100
H'00000400
H'00000100
H'00000100
H'00000100
H'00000100
H'00000100
H'00000100
H'00000600
H'00000600
H'00000600