D6417709SHF200BV Renesas Electronics America, D6417709SHF200BV Datasheet - Page 563
D6417709SHF200BV
Manufacturer Part Number
D6417709SHF200BV
Description
IC SUPER H MPU ROMLESS 208LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.D6417709SBP167BV.pdf
(809 pages)
Specifications of D6417709SHF200BV
Core Processor
SH-3
Core Size
32-Bit
Speed
200MHz
Connectivity
EBI/EMI, FIFO, IrDA, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
96
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.85 V ~ 2.15 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
208-QFP Exposed Pad, 208-eQFP, 208-HQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
D6417709SHF200BV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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16.2
16.2.1
The receive shift register (SCRSR) receives serial data. Data input at the RxD pin is loaded into
SCRSR in the order received, LSB (bit 0) first, converting the data to parallel form. When one
byte has been received, it is automatically transferred to SCFRDR, the receive FIFO data register.
The CPU cannot read or write to SCRSR directly.
16.2.2
The 16-byte receive FIFO data register (SCFRDR) stores serial receive data. The SCIF completes
the reception of one byte of serial data by moving the received data from the receive shift register
(SCRSR) into SCFRDR for storage. Continuous reception is possible until 16 bytes are stored.
The CPU can read but not write to SCFRDR. If data is read when there is no receive data in the
SCFRDR, the value is undefined. When this register is full of receive data, subsequent serial data
is lost.
16.2.3
The transmit shift register (SCTSR) transmits serial data. The SCI loads transmit data from the
transmit FIFO data register (SCFTDR) into SCTSR, then transmits the data serially from the TxD
pin, LSB (bit 0) first. After transmitting one data byte, the SCI automatically loads the next
transmit data from SCFTDR into SCTSR and starts transmitting again. The CPU cannot read or
write to SCTSR directly.
Register Descriptions
Receive Shift Register (SCRSR)
Receive FIFO Data Register (SCFRDR)
Transmit Shift Register (SCTSR)
R/W:
R/W:
R/W:
Bit:
Bit:
Bit:
—
—
R
7
7
7
—
—
R
6
6
6
—
—
R
5
5
5
—
—
R
4
4
4
—
—
R
3
3
3
Rev. 5.00, 09/03, page 517 of 760
—
—
R
2
2
2
—
—
R
1
1
1
—
—
R
0
0
0
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