D6417709SHF200BV Renesas Electronics America, D6417709SHF200BV Datasheet - Page 295
D6417709SHF200BV
Manufacturer Part Number
D6417709SHF200BV
Description
IC SUPER H MPU ROMLESS 208LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.D6417709SBP167BV.pdf
(809 pages)
Specifications of D6417709SHF200BV
Core Processor
SH-3
Core Size
32-Bit
Speed
200MHz
Connectivity
EBI/EMI, FIFO, IrDA, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
96
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.85 V ~ 2.15 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
208-QFP Exposed Pad, 208-eQFP, 208-HQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
D6417709SHF200BV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Bit 15—Area 6 Wait Control (A6W3): Specifies the number of inserted wait states for area 6
combined with bits A6W2–A6W0 in WCR2. Also specifies the number of transfer states in burst
transfer. Clear this bit to 0 when area 6 is not set to PCMCIA.
A6W3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Bit 14—Area 5 Wait Control (A5W3): Specifies the number of inserted wait states for area 5
combined with bits A5W2–A5W0 in WCR2. Also specifies the number of transfer states in burst
transfer. Clear this bit to 0 when area 5 is not set to PCMCIA.
The relationship between the set value and the number of waits is the same as for A6W3.
Bits 13 and 12—Reserved: These bits are always read as 0. The write value should always be 0.
A6W2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
A6W1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
A6W0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Inserted Wait
States
0
1
2
3
4
6
8
10
(Initial value)
12
14
18
22
26
30
34
38
First Cycle
W W W W A A A A I I I I T T T T Pin
Ignored
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Rev. 5.00, 09/03, page 249 of 760
Number of
States per
One-data
Transfer
2
2
3
4
5
7
9
11
13
15
19
23
27
31
35
39
Burst Cycle
W W W W A A A A I I I I T T T T Pin
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
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