D6417709SHF200BV Renesas Electronics America, D6417709SHF200BV Datasheet - Page 426
D6417709SHF200BV
Manufacturer Part Number
D6417709SHF200BV
Description
IC SUPER H MPU ROMLESS 208LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.D6417709SBP167BV.pdf
(809 pages)
Specifications of D6417709SHF200BV
Core Processor
SH-3
Core Size
32-Bit
Speed
200MHz
Connectivity
EBI/EMI, FIFO, IrDA, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
96
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.85 V ~ 2.15 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
208-QFP Exposed Pad, 208-eQFP, 208-HQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
D6417709SHF200BV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Compare Match Constant Register 0 (CMCOR0)
Compare match constant register 0 (CMCOR0) is a 16-bit register that sets the CMCNT0 compare
match period.
CMCOR0 is initialized to H'FFFF by a reset, but retains its previous value in standby mode.
11.4.3
Period Count Operation
When an internal clock is selected with the CKS1 and CKS0 bits in the CMCSR0 register and the
STR bit in CMSTR is set to 1, CMCNT0 begins incrementing on the selected clock. When the
CMCNT counter value matches that of CMCOR0, the CMCNT0 counter is cleared to H'0000 and
the CMF flag in the CMCSR0 register is set to 1. The CMCNT0 counter begins counting up again
from H'0000.
Figure 11.25 shows the compare match counter operation.
Rev. 5.00, 09/03, page 380 of 760
Initial value:
Initial value:
Operation
CMCOR0
R/W:
R/W:
Bit:
Bit:
H'0000
CMCNT0 value
R/W
R/W
15
1
7
1
Figure 11.25 Counter Operation
R/W
R/W
14
1
6
1
R/W
R/W
13
1
5
1
R/W
R/W
Counter cleared by
CMCOR0 compare match
12
1
4
1
R/W
R/W
11
1
3
1
R/W
R/W
10
1
2
1
Time
R/W
R/W
9
1
1
1
R/W
R/W
8
1
0
1
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