D6417709SHF200BV Renesas Electronics America, D6417709SHF200BV Datasheet - Page 144
![IC SUPER H MPU ROMLESS 208LQFP](/photos/12/31/123130/d6417709shf200bv_sml.jpg)
D6417709SHF200BV
Manufacturer Part Number
D6417709SHF200BV
Description
IC SUPER H MPU ROMLESS 208LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.D6417709SBP167BV.pdf
(809 pages)
Specifications of D6417709SHF200BV
Core Processor
SH-3
Core Size
32-Bit
Speed
200MHz
Connectivity
EBI/EMI, FIFO, IrDA, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
96
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.85 V ~ 2.15 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
208-QFP Exposed Pad, 208-eQFP, 208-HQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
D6417709SHF200BV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 144 of 809
- Download datasheet (5Mb)
Rev. 5.00, 09/03, page 98 of 760
Illegal slot instruction
User break point trap
DMA address error
Conditions:
a. When undefined code in a delay slot is decoded
b. When an instruction that rewrites PC in a delay slot is decoded
c. When a privileged instruction in a delay slot is decoded in user mode
Operations: PC of the immediately preceding delay branch instruction is saved to SPC. SR
of the instruction that generated the exception is saved to SSR. H'1A0 is set in EXPEVT.
The BL, MD, and RB bits in SR are set to 1 and a branch occurs to PC = VBR + H'0100.
When an undefined instruction other than H'Fxxx is decoded, operation cannot be
guaranteed.
Conditions: When a break condition set in the user break controller is satisfied
Operations: When a post-execution break occurs, PC of the instruction immediately after
the instruction that set the break point is set in SPC. If a pre-execution break occurs, PC of
the instruction that set the break point is set in SPC. SR when the break occurs is set in
SSR. H'1E0 is set in EXPEVT. The BL, MD, and RB bits in SR are set to 1 and a branch
occurs to PC
Conditions:
a. Word data accessed from addresses other than word boundaries (4n + 1, 4n + 3)
b. Longword accessed from addresses other than longword boundaries (4n + 1, 4n + 2,
Operations: PC of the instruction immediately after the instruction executed before the
exception occurs is saved to SPC. SR when the exception occurs is saved to SSR. H'5C0 is
set in EXPEVT. The BL, MD, and RB bits in SR are set to 1 and a branch occurs to PC
VBR + H'0100.
Delay branch instructions: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT/S,
BF/S
Instructions that rewrite PC: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT, BF,
BT/S, BF/S, TRAPA, LDC Rm, SR, LDC.L @Rm+, SR
Privileged instructions: LDC, STC, RTE, LDTLB, SLEEP; Instructions that access
GBR with LDC/STC are not privileged instructions and therefore do not apply.
4n + 3)
VBR + H'0100. See section 7, User Break Controller, for more information.
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