D6417709SHF200BV Renesas Electronics America, D6417709SHF200BV Datasheet - Page 405
D6417709SHF200BV
Manufacturer Part Number
D6417709SHF200BV
Description
IC SUPER H MPU ROMLESS 208LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.D6417709SBP167BV.pdf
(809 pages)
Specifications of D6417709SHF200BV
Core Processor
SH-3
Core Size
32-Bit
Speed
200MHz
Connectivity
EBI/EMI, FIFO, IrDA, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
96
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.85 V ~ 2.15 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
208-QFP Exposed Pad, 208-eQFP, 208-HQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
D6417709SHF200BV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Bus Modes: There are two bus modes: cycle-steal and burst. Select the mode in the TM bits of
CHCR0–CHCR3.
(16-byte Transfer, External Memory Space (Ordinary Memory)
Cycle-Steal Mode
In cycle-steal mode, the bus is given to another bus master after a one-transfer-unit (byte,
word, longword, or 16-byte unit) DMAC. When another transfer request occurs, the bus is
obtained from the other bus master and transfer is performed for one transfer unit. When that
transfer ends, the bus is passed to the other bus master. This is repeated until the transfer end
conditions are satisfied.
In the cycle-steal mode, transfer areas are not affected regardless of the transfer request source,
transfer source, and transfer destination settings. Figure 11.12 shows an example of DMA
transfer timing in cycle-steal mode. Transfer conditions shown in the figure are:
Dual address mode
DREQ level detection
Figure 11.11 Example of DMA Transfer Timing in Single Address Mode
D31 to D0
A25 to A0
DACKn
CKIO
WEn
CSn
RD
source address
Transfer
DACK)
+4
+8
Rev. 5.00, 09/03, page 359 of 760
+12
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