D6417709SHF200BV Renesas Electronics America, D6417709SHF200BV Datasheet - Page 137
![IC SUPER H MPU ROMLESS 208LQFP](/photos/12/31/123130/d6417709shf200bv_sml.jpg)
D6417709SHF200BV
Manufacturer Part Number
D6417709SHF200BV
Description
IC SUPER H MPU ROMLESS 208LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.D6417709SBP167BV.pdf
(809 pages)
Specifications of D6417709SHF200BV
Core Processor
SH-3
Core Size
32-Bit
Speed
200MHz
Connectivity
EBI/EMI, FIFO, IrDA, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
96
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.85 V ~ 2.15 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
208-QFP Exposed Pad, 208-eQFP, 208-HQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
D6417709SHF200BV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 137 of 809
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4.2.5
When the BL bit in SR is 0, exceptions and interrupts are accepted.
If a general exception event occurs when the BL bit in SR is 1, the CPU’s internal registers are set
to their post-reset state, other module registers retain their contents prior to the general exception,
and a branch is made to the same address (H'A0000000) as for a reset.
If a general interrupt occurs when BL
until the BL bit is cleared to 0 by software. For reentrant exception handling, SPC and SSR must
be saved and the BL bit in SR cleared to 0.
4.2.6
The RTE instruction is used to return from exception handling. When RTE is executed, the SPC
value is set in PC, and the SSR value in SR, and the return from exception handling is performed
by branching to the SPC address.
If SPC and SSR have been saved in external memory, set the BL bit in SR to 1, then restore SPC
and SSR, and issue an RTE instruction.
Exception Type
General interrupt requests
(cont)
Exception Request Masks
Returning from Exception Handling
Exception Event
External hardware interrupts (cont):
IRL3–IRL0 = 0010
IRL3–IRL0 = 0011
IRL3–IRL0 = 0100
IRL3–IRL0 = 0101
IRL3–IRL0 = 0110
IRL3–IRL0 = 0111
IRL3–IRL0 = 1000
IRL3–IRL0 = 1001
IRL3–IRL0 = 1010
IRL3–IRL0 = 1011
IRL3–IRL0 = 1100
IRL3–IRL0 = 1101
IRL3–IRL0 = 1110
1, the request is masked (held pending) and not accepted
Rev. 5.00, 09/03, page 91 of 760
Exception Code
H'240
H'260
H'280
H'2A0
H'2C0
H'2E0
H'300
H'320
H'340
H'360
H'380
H'3A0
H'3C0
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