ATTINY44-15MZ Atmel, ATTINY44-15MZ Datasheet - Page 118

• Manufacturer Part Number: ATTINY44-15MZ
• Description: MCU AVR 4K FLASH 15MHZ 20-QFN
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY44-15MZ

• Package / Case: 20-QFN Exposed Pad
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Speed: 16MHz
• Number Of I /o: 12
• Eeprom Size: 256 x 8
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Program Memory Size: 4KB (4K x 8)
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Connectivity: USI
• Core Size: 8-Bit
• Processor Series: ATTINY4x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: SPI, UART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 12
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

14.11.7
14.11.8
118
Atmel ATtiny24/44/84 [Preliminary]
ICR1H and ICR1L – Input Capture Register 1
TIMSK1 – Timer/Counter Interrupt Mask Register 1
The Input Capture is updated with the counter (TCNT1) value each time an event occurs on
the ICP1 pin (or optionally on the Analog Comparator output for Timer/Counter1). The Input
Capture can be used for defining the counter TOP value.
The input capture register is 16 bits in size. To ensure that both the high and low bytes are
read simultaneously when the CPU accesses these registers, the access is performed using
an 8-bit temporary high byte register (TEMP). This temporary register is shared by all the other
16-bit registers.
• Bit 7,6,4,3 – Reserved Bit
This bit is reserved for future use. For ensuring compatibility with future devices, this bit must
be written to logical zero when the register is written.
• Bit 5 – ICIE1: Timer/Counter1, Input Capture Interrupt Enable
When this bit is written to logical one and the I-flag in the status register is set (interrupts glob-
ally enabled), the timer/counter 1 input capture interrupt is enabled. The corresponding inter-
rupt vector (see
ICF1 Flag, located in TIFR1, is set.
• Bit 2– OCIE1B: Timer/Counter1, Output Compare B Match Interrupt Enable
When this bit is written to logical one and the I-flag in the status register is set (interrupts glob-
ally enabled), the timer/counter 1 output compare B match interrupt is enabled. The
corresponding interrupt vector (see
located in TIFR1, is set.
• Bit 1– OCIE1A: Timer/Counter1, Output Compare A Match Interrupt Enable
When this bit is written to logical one and the I-flag in the status register is set (interrupts glob-
ally enabled), the timer/counter 1 output compare A match interrupt is enabled. The
corresponding interrupt vector (see
located in TIFR1, is set.
• Bit 0 – TOIE1: Timer/Counter1, Overflow Interrupt Enable
When this bit is written to logical one and the I-flag in the status register is set (interrupts glob-
ally enabled), the timer/counter 1 overflow interrupt is enabled. The corresponding interrupt
vector (see
Bit
0x25 (0x45)
0x24 (0x44)
Read/Write
Initial Value
Bit
0x0C (0x2C)
Read/Write
Initial Value
“Interrupts” on page
R/W
“Accessing 16-bit Registers” on page
“Interrupts” on page
R
7
0
7
–
0
R/W
R
6
0
6
–
0
50) is executed when the TOV1 flag, located in TIFR1, is set.
ICIE1
R/W
R/W
5
0
5
0
“Interrupts” on page
“Interrupts” on page
50) is executed when the
R/W
4
0
R
4
–
0
ICR1[15:8]
ICR1[7:0]
R/W
3
0
R
3
–
0
94.
50) is executed when the OCF1B flag,
50) is executed when the OCF1A flag,
OCIE1B
R/W
R/W
2
0
2
0
OCIE1A
R/W
R/W
1
0
1
0
R/W
TOIE1
R/W
0
0
0
0
7701E–AVR–02/11
ICR1H
TIMSK1
ICR1L