ATTINY44-15MZ Atmel, ATTINY44-15MZ Datasheet - Page 52

• Manufacturer Part Number: ATTINY44-15MZ
• Description: MCU AVR 4K FLASH 15MHZ 20-QFN
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY44-15MZ

• Package / Case: 20-QFN Exposed Pad
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Speed: 16MHz
• Number Of I /o: 12
• Eeprom Size: 256 x 8
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Program Memory Size: 4KB (4K x 8)
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Connectivity: USI
• Core Size: 8-Bit
• Processor Series: ATTINY4x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: SPI, UART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 12
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

11. External Interrupts
11.1
52
Pin Change Interrupt Timing
Atmel ATtiny24/44/84 [Preliminary]
The external interrupts are triggered by the INT0 pin or any of the PCINT11..0 pins. Observe
that, if enabled, the interrupts will trigger even if the INT0 or PCINT11..0 pins are configured as
outputs. This feature provides a way of generating a software interrupt. Pin change 0 inter-
rupts (PCI0) will trigger if any enabled PCINT7..0 pin toggles. Pin change 1 interrupts (PCI1)
will trigger if any enabled PCINT11..8 pin toggles. The PCMSK0 and PCMSK1 registers con-
trol which pins contribute to the pin change interrupts. Pin change interrupts on PCINT11..0
are detected asynchronously. This implies that these interrupts also can be used for waking
the part from sleep modes other than idle mode.
The INT0 interrupts can be triggered by a falling or rising edge or a low level. This is set up as
indicated in the specification for the MCU control register (MCUCR). When the INT0 interrupt
is enabled and is configured as level-triggered, the interrupt will trigger as long as the pin is
held low. Note that recognition of falling- or rising-edge interrupts on INT0 requires the pres-
ence of an I/O clock, described in
interrupt on INT0 is detected asynchronously. This implies that this interrupt also can be used
for waking the part from sleep modes other than idle mode. The I/O clock is halted in all sleep
modes except idle mode.
Note that if a level-triggered interrupt is used for wake-up from power-down, the required level
must be held long enough for the MCU to complete the wake-up to trigger the level interrupt. If
the level disappears before the end of the start-up time, the MCU will still wake up, but no
interrupt will be generated. The start-up time is defined by the SUT and CKSEL fuses as
described in
An example of timing of a pin change interrupt is shown in
Figure 11-1. Timing of pin change interrupts
pcint_setflag
pcint_in_(0)
PCINT(0)
pcint_syn
pin_sync
“System Clock and Clock Options” on page
pin_lat
PCINT(0)
PCIF
clk
clk
LE
pin_lat
D
Q
pin_sync
“Clock Systems and their Distribution” on page
PCINT(0) in PCMSK(x)
pcint_in_(0)
0
x
clk
25.
Figure
pcint_syn
11-1.
pcint_setflag
PCIF
7701E–AVR–02/11
25. Low level