ATTINY44-15MZ Atmel, ATTINY44-15MZ Datasheet - Page 70
![MCU AVR 4K FLASH 15MHZ 20-QFN](/photos/12/32/123214/20-qfn-pc_sml.jpg)
ATTINY44-15MZ
Manufacturer Part Number
ATTINY44-15MZ
Description
MCU AVR 4K FLASH 15MHZ 20-QFN
Manufacturer
Atmel
Series
AVR® ATtinyr
Datasheet
1.ATTINY44-15MZ.pdf
(225 pages)
Specifications of ATTINY44-15MZ
Package / Case
20-QFN Exposed Pad
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Operating Temperature
-40°C ~ 125°C
Speed
16MHz
Number Of I /o
12
Eeprom Size
256 x 8
Core Processor
AVR
Program Memory Type
FLASH
Ram Size
256 x 8
Program Memory Size
4KB (4K x 8)
Data Converters
A/D 8x10b
Oscillator Type
Internal
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Connectivity
USI
Core Size
8-Bit
Processor Series
ATTINY4x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
SPI, UART
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
12
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATTINY44-15MZ
Manufacturer:
ATMEL
Quantity:
1 000
Part Number:
ATTINY44-15MZ
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
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12.4
12.4.1
12.4.2
70
Register Description
Atmel ATtiny24/44/84 [Preliminary]
MCUCR – MCU Control Register
PORTA – Port A Data Register
Table 12-9.
1.
2.
.
• Bit 6 – PUD: Pull-up Disable
When this bit is written to logical one, the pull-ups in the I/O ports are disabled even if the
DDxn and PORTxn registers are configured to enable the pull-ups ({DDxn, PORTxn} = 0b01).
See
Bit
Read/Write
Initial Value
Bit
0x1B (0x3B)
Read/Write
Initial Value
Signal
Name
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
PTOE
DIEOE
DIEOV
DI
AIO
“Configuring the Pin” on page 57
EXT_OSC = crystal oscillator or low frequency crystal oscillator is selected as system clock.
EXT_CLOCK = external clock is selected as system clock.
PB1/XTAL2/PCINT9
EXT_OSC
0
EXT_OSC
0
EXT_OSC
0
0
EXT_OSC
PCINT9 • PCIE1
EXT_OSC
PCINT9 Input
XTAL2
PORTA7
BODS
Overriding Signals for Alternate Functions in PB1..PB0
R/W
R/W
7
0
7
0
(1)
(1)
(1)
(1)
(1)
PORTA6
+
• PCINT9 • PCIE1
PUD
R/W
R/W
6
0
6
0
PORTA5
R/W
R/W
5
0
SE
5
0
for more details about this feature.
PORTA4
R/W
4
0
SM1
R/W
4
0
PB0/XTAL1/PCINT8
EXT_CLOCK
0
EXT_CLOCK
0
EXT_CLOCK
0
0
EXT_CLOCK
(PCINT8 • PCIE1)
(EXT_CLOCK
(EXT_CLOCK
CLOCK/PCINT8 Input
XTAL1
PORTA3
R/W
3
0
SM0
R/W
3
0
(2)
(2)
(2)
(2)
(2)
(2)
PORTA2
R/W
+ EXT_OSC
+ EXT_OSC
+ EXT_OSC
BODSE
+ EXT_OSC
• PWR_DOWN ) +
• EXT_OSC
2
0
R/W
2
0
PORTA1
R/W
ISC01
1
0
R
1
0
(1)
(1)
(1)
(1)
(1)
+
• PCINT8 • PCIE1)
PORTA0
ISC00
R/W
0
0
R
0
0
7701E–AVR–02/11
MCUCR
PORTA
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