ATTINY44-15MZ Atmel, ATTINY44-15MZ Datasheet - Page 124

• Manufacturer Part Number: ATTINY44-15MZ
• Description: MCU AVR 4K FLASH 15MHZ 20-QFN
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY44-15MZ

• Package / Case: 20-QFN Exposed Pad
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Speed: 16MHz
• Number Of I /o: 12
• Eeprom Size: 256 x 8
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Program Memory Size: 4KB (4K x 8)
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Connectivity: USI
• Core Size: 8-Bit
• Processor Series: ATTINY4x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: SPI, UART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 12
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

124
Atmel ATtiny24/44/84 [Preliminary]
Figure 16-3. Three-wire Mode, Timing Diagram
The Three-wire mode timing is shown in
USCK cycle reference. One bit is shifted into the USI shift register (USIDR) for each of these
cycles. The USCK timing is shown for both external clock modes. In external clock mode 0
(USICS0 = 0), DI is sampled at positive edges, and DO is changed (data register is shifted by
one) at negative edges. External clock mode 1 (USICS0 = 1) uses the opposite edges versus
mode 0, i.e., it samples data at negative edges and changes the output at positive edges. The
USI clock modes correspond to the SPI data mode 0 and 1.
Referring to the timing diagram
ing steps:
1. The slave device and master device set up their data output and, depending on the
2. The Master generates a clock pulse by software toggling the USCK line twice (C and
3. Step 2 is repeated eight times for a complete register (byte) transfer.
4. After eight clock pulses (i.e., 16 clock edges), the counter will overflow and indicate that
protocol used, enable their output driver (mark A and B). The output is set up by writing
the data to be transmitted to the serial data register. Enabling of the output is done by
setting the corresponding bit in the port data direction register. Note that points A and B
do not have any specific order, but both must be at least one half USCK cycle before
point C, where the data are sampled. This must be done to ensure that the data setup
requirement is satisfied. The 4-bit counter is reset to zero.
D). The bit value on the slave and master’s data input (DI) pin is sampled by the USI on
the first edge (C), and the data output is changed on the opposite edge (D). The 4-bit
counter will count both edges.
the transfer is completed. The data bytes transferred must now be processed before a
new transfer can be initiated. The overflow interrupt will wake up the processor if it is
set to idle mode. Depending on the protocol used, the slave device can now set its out-
put to high impedance.
CYCLE
USCK
USCK
DO
DI
( Reference )
A
B
MSB
MSB
C
1
D
2
6
6
(Figure 16-3 on page
3
5
5
Figure 16-3 on page
4
4
4
124), a bus transfer involves the follow-
5
3
3
6
124. At the top of the figure is a
2
2
7
1
1
LSB
LSB
8
7701E–AVR–02/11
E